TESTING OF DIGITAL CIRCUITS
vonJunhao Shi
Dissertation
zur Erlangung des akademischen Grades eines Doktors der Ingenieurwissenschaften
Dr.Ing.
-Vorgelegt im Fachbereich 3 (Mathematik & Informatik) der Universit¨at Bremen
Gutachter : P rof.Dr. Rolf Drechsler P rof.Dr. J an P eleska
Table of Contents iii List of Tables vi List of Figures ix Abstract xi Acknowledgements xiii 1 Introduction 1 1.1 Problem Description . . . 1 1.1.1 ATPG . . . 2
1.1.2 Synthesis for Testability . . . 5
1.2 Contributions of this Thesis . . . 6
2 Preliminaries 11 2.1 Boolean Techniques . . . 11
2.1.1 Boolean Functions . . . 11
2.1.2 Binary Decision Diagrams . . . 13
2.1.3 SAT Problem . . . 16
2.2 Digital Circuits . . . 20
2.2.1 Combinational Logic Circuits . . . 20
2.2.2 BDD Circuits . . . 22
2.2.3 Circuits with Tri-state Elements . . . 23
2.3 Fault Models . . . 26
2.3.1 Stuck At Fault Model . . . 27
2.3.2 Path Delay Fault Model . . . 28
2.3.3 Bridging Fault Model . . . 29 iii
2.4.3 ATPG Systems . . . 35
3 Testing of BDD Circuits 39 3.1 Introduction . . . 39
3.2 ATPG in Polynomial Time . . . 41
3.2.1 BDD Circuits of General Boolean Functions . . . 41
3.2.2 BDD Circuits of Symmetric Function . . . 53
3.3 Testability of BDD Circuits . . . 54
3.3.1 BDD Transformation . . . 54
3.3.2 Testability Under the Stuck At Fault Model . . . 57
3.3.3 Testability Under the Path Delay Fault Model . . . 57
3.3.4 Testability under the Bridging Fault Model . . . 60
3.3.5 Partial Simplification . . . 62
3.3.6 Experimental Results . . . 64
3.4 Optimization of BDD Circuits . . . 71
3.4.1 Sifting with Different Objective Functions . . . 71
3.4.2 Experimental Results . . . 73
4 SAT based ATPG for Industrial Circuits 79 4.1 Introduction . . . 80
4.2 Encoding for Tri-state Circuits . . . 81
4.2.1 Four-Valued Logic . . . 81
4.2.2 Boolean Encoding . . . 82
4.2.3 Transformation to SAT Instance . . . 83
4.2.4 Experimental Results for ATPG . . . 86
4.3 SAT-based ATPG . . . 89
4.3.1 D-Algorithm . . . 89
4.3.2 Encoding . . . 93
4.3.3 Variable Selection . . . 94
4.3.4 Experimental Results . . . 97
4.4 Combination with Classical TPG . . . 105
4.4.1 Classical Test Generation . . . 106
4.4.2 Combination . . . 108
4.4.3 Experimental Results . . . 110
5 Conclusion 117
2.1 4-valued AND gate . . . 25
2.2 Truth table of 3-state BUS . . . 26
2.3 Truth table of 3-state BUS0 . . . 26
2.4 Truth table of 3-state BUS1 . . . 27
3.1 Detect function for SAF . . . 42
3.2 Classical approaches . . . 66
3.3 Path delay fault coverage of BDD circuits . . . 66
3.4 Path delay fault coverage of the BDD circuit for symmetric function . 67 3.5 Comparison with earlier works . . . 68
3.6 Test pattern generation for benchmark circuits . . . 70
3.7 BDD statistics . . . 74
3.8 Results for the circuits . . . 74
3.9 Path delay fault coverage of optimized BDD circuits . . . 76
3.10 Circuits optimized by sifting for RPT . . . 77
4.1 Boolean encodings . . . 82
4.2 AND gate over {0, 1, Z, U} . . . . 84
4.3 Number of clauses for each encoding . . . 85
4.4 Number of gates for each type . . . 86
4.5 Memory and run time for different encodings . . . 87
4.6 Representation of a gate in CNF . . . 91
4.7 Encoding of the 4-valued domain . . . 92 vii
4.10 CNF size for a 2-input AND gate . . . 93
4.11 Results for the Boolean circuit model . . . 100
4.12 Results for the 4-valued circuit model . . . 101
4.13 PASSAT with different variable selection strategies . . . 102
4.14 PASSAT for industrial benchmarks . . . 103
4.15 Run-Time of different SAT solvers . . . 104
4.16 Time to classify faults . . . 104
4.17 Runtime of FAN and SAT . . . 112
4.18 Pre-identification results(1) . . . 113
4.19 Pre-identification results(2) . . . 114
4.20 the number of test patterns of FAN and SAT . . . 115
1.1 Design Flow . . . 2
2.1 BDD for the function f = x1· x2+ x3 . . . 14
2.2 Type 1 reduction rule . . . 16
2.3 Type 2 reduction rule . . . 16
2.4 Multiplexer cell MUX of AND, OR, and INVERTER . . . 21
2.5 PTL multiplexer as wired OR of two NMOS transistors . . . 21
2.6 Mapping a BDD to a circuit . . . 22
2.7 BDD circuit over MUXLIB . . . 23
2.8 BDD circuit over STD . . . 24
2.9 Element and truth table of DRIV bus-driver . . . 25
2.10 Element and truth table of NDRIV bus-driver . . . 25
2.11 Stuck at fault . . . 28
2.12 Bridging fault . . . 30
2.13 Main inputs and outputs of the ATPG process . . . 31
2.14 Example circuit with a SA1 fault and a test for it . . . 33
2.15 General structure of the state-of-the-art of ATPG systems . . . 35
3.1 Calculation of paths . . . 47
3.2 Example for the calculations of paths . . . 47
3.3 Test pattern generation for BF . . . 49
3.4 Propagation, if level(g) > level(h) . . . . 51
3.5 Feedback loop . . . 51 ix
3.8 BDD for symmetric function S2(1, 2) . . . . 54
3.9 Example for transformation . . . 55
3.10 Example for right data input constant 1 . . . 62
3.11 Example for right data input constant 0 . . . 63
3.12 Example for left data input constant 0 . . . 64
3.13 Example for left data input constant 1 . . . 65
4.1 Example network fragment from [85] . . . 91
4.2 Basic loop of a SAT solver . . . 94
4.3 Redundancies: conflicts vs. time . . . 97
4.4 General structure of the new ATPG system . . . 109
Currently, Very Large Scale Integrated (VLSI) circuits and the resulting digital sys-tems are widely used in almost all areas of human’s life. To ensure the validity of these systems, error-free VLSI circuits are becoming more and more important. With the increasing complexity of VLSI circuits, the cost for the test on VLSI circuits has risen dramatically. So it is necessary to reduce the cost of test. This thesis pro-poses two approaches to achieve this goal. One approach, used before manufacture, is to improve the circuit structure for a better testability. The other one, used after manufacture, is to improve the test tool for a higher efficiency of fault detection.
In this thesis, Binary Decision Diagrams (BDDs) are used to improve the structure of VLSI circuits for a better testability. It has been proved that Automatic Test Pat-tern Generation (ATPG) for BDD circuits under the Stuck At Fault Model (SAFM), the Path Delay Fault Model (PDFM) and the Bridging Fault Model (BFM) can be carried out in polynomial time. A new technique that adds a new input and an in-verter to BDD circuits has been presented. Using this technique, the testability of circuits under SAFM, PDFM and BFM can be greatly improved. Especially, under SAFM and PDFM, 100% testable circuits can be generated.
On the other hand, a technique based on Boolean Satisfiability (SAT) is proposed to improve the efficiency of test tools. A SAT-based ATPG algorithm suited for large industrial circuits with tri-state elements has been presented. It can generate test patterns for the faults that are aborted by classical algorithms. The combination of a classical TPG stage and the SAT-based TPG stage has been integrated into an industrial ATPG tool. Experimental results have demonstrated the quality and efficiency of this combination.
I would like to thank Rolf Drechsler, my supervisor, who has been an invaluable source of wisdom and inspiration, for his many suggestions and constant support during this research. His encouragement, enthusiasm for new ideas and constant pursuit of the best possible solution to the problems met have been fundamental in the achievement of the results presented in this thesis. I am deeply indebted to him.
Special thanks should be given to G¨orschwin Fey and Daniel Tille for sharing the opinion in many interesting technical discussions. Many thanks are also due to all the colleagues in our AGRA group who are always friendly and ready to given me help.
Thanks to the involved people at Philips Semiconductor GmbH Hamburg, espe-cially to Andreas Glowatz, Friedrich Hapke and J¨urgen Schl¨offel for the fruitful dis-cussions we had and all the supports.
Of course, I am grateful to my parents for their patience and love. Without them this work would never have come into existence (literally).
Finally, I would like to express complete gratitude to my wife, Hua Chen. Her prompting started me down this academic journey. It is her endless support and sacrifices over the years that made this journey more enjoyable. I wish both to thank and to dedicate this dissertation to her for all of the love that she brings to my life.
Bremen Junhao Shi
September, 2006
Introduction
Very Large Scale Integrated (VLSI) circuits and the resulting digital systems are used in mobile telephones, in TVs, in cars, in almost all areas of our life. Com-plex digital systems are controlling whole factories, airplanes, banks, even our whole country. Hence, error-free VLSI circuits are becoming more and more important. Even if a circuit is correctly designed, a fraction of them may behave faulty because of physical defects caused by imperfections during the manufacturing process. So post-production test is very important.
VLSI circuit are becoming more and more complex. In 1965 Gordon Moore pre-dicted famous Moore’s Law [61] that the transistor density of semiconductor chips would double roughly every 18 months. With increasing complexity of VLSI circuits, the costs for the test phase have risen dramatically, at least 25% and up to 60-70% of the total product costs account for testing [60, 92]. Thus the topics of this thesis is finding new methods to reduce the cost of test.
1.1
Problem Description
Figure 1.1 shows the VLSI circuit design flow. At first, a requirement is specified, then it is written in a formal format, then it is synthesized to gate-level, the following
Specification Formal description Synthesis Layout Manufacture Verification Test
Figure 1.1. Design Flow
step is design layout. If the design is correct, this design is sent to manufacture. At last test tools are used to check if the product is fully correct. From this flow, we can see that there are two ways to reduce the cost of test:
1. After manufacturing, by improving the test tools to find the faults efficiently.
2. Before manufacturing, by improving the structure of the circuit, using synthesis algorithms to generate circuits that have good testability.
In the following, the problem is described in these two ways.
1.1.1 ATPG
The test ensures the functional correctness of a chip and is therefore an important step in ensuring high quality products. In practice the post-production test is carried out by applying input stimuli - a so called “test pattern” - to the circuit and controlling the output response with respect to its correctness. The test patterns are calculated during Automatic Test Pattern Generation (ATPG).
Usually, a fault model is used to model physical defects at the functional level in a Boolean representation of the circuit. Then, the space of input stimuli is searched to find a test pattern for a particular fault. Among the fault models the Stuck At Fault Model (SAFM) is most frequently used in practice.
A complete state-of-the-art ATPG system start with preprocesses, among which there are fault collapsing, and static learning. Next, a random TPG stage, limited by certain stop-criteria, generates tests for the easy-to-detect faults. Thereafter, one or more deterministic ATPG stages try to find tests for the remaining faults. Finally, test set compaction is applied.
Building a more efficient deterministic ATPG stage into the ATPG system can improve the efficient of the whole system. The D-algorithm [68] was the first de-terministic ATPG algorithm to carry out an efficient back track search steered by structural information from the circuit. The algorithms PODEM [38] and FAN [36] improved the branching heuristics to make the search more efficient. Using structural information to apply global implications during the search has been proposed for SOCRATES [73]. The more powerful recursive learning [49, 50] and the integration with FAN-algorithm have been proposed for the tool HANNIBAL [48]. However, due to the ever increasing size of integrated circuits, those classical algorithms reach their limits.
While classical approaches are based on backtracking on the circuit structure, since the early 80s several approaches based on Boolean Satisfiability (SAT) have been pro-posed (see e.g. [85, 82, 87, 86]). In [85] comparisons to more than 40 other “classical” approaches based on FAN, PODEM, and the D-algorithm are provided showing the robustness and effectiveness of SAT-based techniques. In contrast to the early work
in the 80s, where ATPG was often reduced to PROLOG or logic programming, the ATPG techniques developed by Larrabee [51] and Stephan et al. [85] used many simplification and learning approaches, like global implications [87]. By this, these algorithms combined the power of SAT with algorithms from the testing domain. These tools transform the problem of ATPG into a SAT problem. This SAT instance is then solved by a dedicated SAT solver. The solver either proves unsatisfiability, i.e. the fault is redundant, or generates a satisfying assignment, i.e. a test pattern. But those SAT approaches only considered Boolean values so they are not able to handel industrial circuits which have tri-state values. So it is necessary to study the problem for a multi-value logic encoding, i.e. the ATPG tool can also consider unknown values and tri-states.
Recently, there is a renewed interest in SAT, algorithms for SAT have been dramat-ically improved. This is due to the use of several advanced techniques in SAT solvers: the DLL procedure [22], dynamic learning [58], efficient implementation techniques [62], and robust search heuristics [39]. These modern SAT solvers have been applied with success to search problems in different areas, e.g. artificial intelligence or for-mal verification. The combination of these advanced SAT technique and structural knowledge into an ATPG tool will be helpful.
Of course it can not be expected that a single SAT-based deterministic ATPG stage is faster on all ATPG instances than the classical approaches. So the combination with other deterministic ATPG stage should be considered.
1.1.2 Synthesis for Testability
On the other hand, we can improve the structure of circuits to reduce the cost of the test phase, i.e. testability issues should be considered from the very beginning of the design process that guarantee the testability of the circuit at the end of the manufacturing process.
Binary Decision Diagrams (BDDs) [17] have originally been proposed as a data structure for efficient Boolean function representation and manipulation. Specifically in formal verification and logic synthesis, BDDs have become the state-of-art for func-tion representafunc-tion and manipulafunc-tion [18]. BDDs have also been frequently used in logic synthesis approaches since they allow to combine aspects of circuit synthesis and technology mapping [41]. Recently, there has been a renewed interest in multiplexor-based design styles, since multiplexor nodes can be realized at very low cost, e.g. in Pass Transistor Logic (PTL). BDD approaches are especially suitable for multiplexor based design styles, since the circuits can be directly derived from BDDs if each in-ternal node is substituted by a multiplexor cell. One further important argument for the use of BDD circuits are the testability aspects. Due to the structural restrictions of BDDs, testability can be ensured by construction. Multiplexor circuits derived from BDDs have been studied intensively under various fault models which cover a wide range of the possible defects [9, 8, 11, 10]. (For an overview see [12].) However, none of these approaches can guarantee 100% testability in a “systematic way”. For instance, in [11], an algorithm is given that can compute all redundancies of a circuit in polynomial time, but the removal of these redundancies can generate new ones (so-called second generation redundancies). For their removal, only classical ATPG can be applied. So it will be very useful, if we can find a way to get a full testable
BDD circuit and at the same time, BDD operation can be used in ATPG.
1.2
Contributions of this Thesis
In this thesis the two Boolean techniques BDD and SAT are used in testing of digital circuits. Circuits derived from BDDs have a better structure for testing, and ATPG for BDD circuits can be carried out in polynomial time. SAT techniques have been used in ATPG of industrial digital circuits in this thesis. SAT-based ATPG can classify most of faults that are aborted from classical FAN ATPG algorithms.
Firstly, synthesis algorithms to improve the testability of BDD circuits are intro-duced. A simple transformation, adding a new INPUT and an INVERTER to a BDD circuit, is presented. This guarantees full testability of the BDD circuit under the Stuck At Fault Model (SAFM) [1] and the robust Path-Delay Fault Model (PDFM) [10, 26]. By shifting the BDD variable order, the BDD circuit can be optimized. This can not only reduce the size of the BDD circuit, but also improve the testabil-ity of BDD circuits. Although the SAFM and PDFM are the standard fault model, frequently occurring faults in some technologies are unintentional shorts, denoted as Bridging Faults (BFs) [7, 31]. So increasing attention has been given to the area of modeling and testing of BFs [89, 54]. For circuits derived from BDDs the complete test pattern generation process for BFs is formulated in terms of symbolic BDD ma-nipulations. These symbolic operations allow to consider all possible test patterns at the same time. So ATPG of BDD circuits for BFs can be carried out in polynomial time. And the new technique (adding a new INPUT and INVERTER) improves the testability of the BDD circuit under Bridging Fault Model (BFM) although it cannot guarantee full testability. Through improving the testability of circuits, the circuit can be tested easier, so the test cost can been reduced.
Secondly, an efficient SAT-based ATPG algorithm is presented. The algorithm has been implemented as the tool PASSAT (PAttern Search using SAT). It makes use of techniques recently developed for SAT solvers and so far only applied in the verifica-tion domain. In contrast to previous SAT approaches, that only considered Boolean values, we study the problem for a multi-valued logic encoding, i.e. our ATPG tool can also consider unknown values and tri-states. The influence of different branching heuristics is studied to tune the SAT solver towards test generation, i.e. variable se-lection strategies known from SAT and strategies applied in classical ATPG [38, 36]. The algorithm has been combinated with classical TPG algorithm in our ATPG sys-tem. Only the faults that aborted from classical TPG attend the SAT-ATPG stage. Then the new ATPG system can benefit from the classical ATPG process and the SAT technique. So this system can detect more faults and reduce the test time, it reduces the test cost.
Parts of this thesis have been published:
1. Junhao Shi, G¨orschwin Fey, Rolf Drechsler, Andreas Glowatz, J¨urgen Schl¨offel, Friedrich Hapke, “Experimental Studies on SAT-based Test Pattern Generation for Industrial Circuits”, The 6th international Conference on ASIC (ASICON 2005), p967-970, Shanghai, China, 2005
2. Junhao Shi, G¨orschwin Fey, Rolf Drechsler, Andreas Glowatz, Friedrich Hapke, J¨urgen schl¨offel, “PASSAT: Efficient SAT-based Test Pattern Generation”, IEEE Annual Symposium on VLSI (ISVLSI 2005), p212-217, Tampa Florida, USA, 2005
3. G¨orschwin Fey, Junhao Shi, Rolf Drechsler, ”Efficiency of Multiple-Valued En-coding in SAT-based ATPG”, IEEE International Symposium on Multiple-Valued Logic (ISMVL 2006), p25, Singapore, 2006
4. Junhao Shi, G¨orschwin Fey, Rolf Drechsler “Bridging Fault Testability of BDD Circuits”, Asia and South Pacific Design Automation Conference 2005 (ASP-DAC 2005), p188-191, Shanghai, China, 2005
5. Rolf Drechsler, Junhao Shi, G¨orschwin Fey, “Synthesis of Fully Testable Circuits from BDDs”, IEEE Transaction on Computer-Aided Design, p440-443, 2004
6. Junhao Shi, G¨orschwin Fey, Rolf Drechsler “Experimental Studies on Test Pat-tern Generation for BDD Circuits”, InPat-ternational Workshop on Boolean Prob-lems (IWSBP 2004), p71-76, Freiberg, Germany, 2004
7. Rolf Drechsler, Junhao Shi, G¨orschwin Fey, “MuTaTe: An Efficient Design for Testability Technique for Multiplexor based Circuits”, IEEE Great Lakes Symposium on VLSI (GLSV 2003), p80-83, Washington, USA, 2003
8. Junhao Shi, G¨orschwin Fey, Rolf Drechsler, “BDD based Synthesis of Symmetric Functions with Full Path-Delay Fault Testability”, IEEE Twelfth Asian Test Symposium (ATS 2003), p290-293, Xi’an, China, 2003
9. Junhao Shi, G¨oschwin Fey, Rolf Drechsler, “Random Pattern Testability of Circuits Derived from BDDs”, 4th Workshop on RTL and High Level Testing (WRTLT 2003), p70-78, Xi’an, China, 2003
Michael Wittke “Integration of SAT-based ATPG in an Industrial Environ-ment”, submitted.
This thesis is structured as follows: After Chapter 1, this introduction, in Chapter 2 basic notations and definitions are given. The testability of circuits derived from BDD is studied in Chapter 3. An efficient SAT-based ATPG algorithm is presented in Chapter 4. Chapter 5 summarizes the work in this thesis.
Preliminaries
In this chapter some concepts of Boolean techniques, digital circuits and test of dig-ital circuits are defined, as far as they are used in the following chapters. Firstly, Boolean Functions, Binary Decision Diagrams (BDDs) and the Boolean Satisfiabil-ity Problem (SAT) are introduced. Then combinational logic circuits, BDD circuits and tri-state circuits are explained, and fault models to model physical defects at the functional level in those circuits are defined. Finally a general Automatic Test Pattern Generation (ATPG) flow is presented.
2.1
Boolean Techniques
2.1.1 Boolean Functions
Boolean functions are used to describe the digital logic of a circuit. A circuit transforms inputs, i.e. a vector of incoming Boolean signals to a vector of outputs, thereby following a certain specification. This specification can be described by a Boolean function.
Suppose that IN∧ denotes the set of natural numbers not including zero, i.e. IN = 11
{1, 2, . . .}. Let IB := {0, 1} and n ∈ IN. Boolean variables, typically denoted by Latin letters. Generally, variables are referred to by subscripts which are from the set {1, 2, . . . , n}, e.g. x1, x2, . . . , xn. The notation Xn is used to denote the set {x1, x2, . . . , xn} of “standard” variables.
Definition 2.1.1. Let m, n ∈ IN. A mapping f : IBn −→ IBm is called a Boolean function. In the case of m = 1 we say f is a single-output function, otherwise f is called a multi-output function. Let f (x1, x2, . . . , xn) denote a Boolean function of n Boolean variables. A minterm is a product of variables in which every variable appears once. The weight w of a minterm is defined as the number of uncomplemented variables that appear in the minterm.
Symmetric Boolean functions often appear in logic design [45], and are widely used in cryptology [24, 94]. The definition of the symmetric Boolean functions is given in the following.
Definition 2.1.2. A Boolean function f (x1, x2, . . . , xn) is totally symmetric with respect to the variables (x1, x2, . . . , xn) if it is invariant under any permutation of the variables [45]. Total symmetry can be expressed in terms of a set of integers (called a-numbers [20]) A ={ai, . . . , aj, . . . , ak}, where A ⊆ {0, 1, 2, . . . , n}. All the vertices with weight w ∈ A will appear as true minterms in the function. An n-variables symmetric function is denoted as Sn(ai, . . . , aj, . . . , ak) [67]. For n variables, 2n+1 totally symmetric functions exist.
Definition 2.1.3. Let f (x1, . . . , xn) be a Boolean function. Then
fxi = f (x1, . . . , xi−1, xi = 1, xi+1, . . . , xn) fxi = f (x1, . . . , xi−1, xi = 0, xi+1, . . . , xn)
are positive and negative cofactor of function f with respect to xi.
Theorem 2.1.1 (Shannon decomposition). Let f : Bn−→ Bm be a Boolean function (over Xn). For all xn∈ Xn, we have:
f = xi· fxi+ xi· fxi
fxi and fxi are positive and negative cofactor of the function f with respect to xi.
2.1.2 Binary Decision Diagrams
Many applications in VLSI CAD make use of reduced ordered BDDs as introduced in [17]:
A BDD is a graph-based data structure. A Boolean function f : IBn −→ IBm can be represented by a BDD which is an acyclic graph where the Shannon decomposition is carried out at each node. A BDD is called ordered if each variable is encountered at most once and in the same order on each path from the root to the terminal node. A BDD is called reduced if it does not contain isomorphic subgraphs nor does it have redundant nodes. Reduced and ordered BDDs are a canonical representation i.e. for each Boolean function the BDD is uniquely specified. More formal, the definition is given as follows:
Definition 2.1.4. An Ordered Binary Decision Diagram (OBDD) is a tuple (π, G, O)
where π denotes the variable ordering of the OBDD and G is a finite Directed Acyclic Graph (DAG) G = (V, E) (V denotes the set of vertices and E denotes the set of edges of the DAG) with multi-root nodes (denoted roots). O ∈ V is a finite set of root nodes O ={o1, o2, . . . , om}. An OBDD has the following properties:
X X X 3 2 1 0 1 f v1 v v 2 3 v v t0 t1 level 2 level 3 level 4 level 1
Figure 2.1. BDD for the functionf = x1 · x2+ x3
• Each non-terminal node v is labeled with a variable xi ∈ Xn, denoted by var(v) (for terminal nodes, var(v) denotes the value of the node: 0 or 1), and has exactly two child nodes in V which are positive and negative cofactor of the node’s function and are denoted by high(v) and low(v), respectively.
• On each path from the root node to a terminal node, the variables are encoun-tered at most once and in the same order.
• Each root node of the component OBDD graphs must be contained in O.
Based on the variable order (x1, x2, . . . , xn), a level is assigned to each node v, where
level(v) =
i if v is a non-terminal node and label(v) = xi n + 1 if v is a terminal node
A node with level(v) = 1 is on the highest level, while terminal nodes are on the lowest level.
Example 1. In Figure 2.1, a BDD for the function f = x1 · x2 + x3 is shown.
level(v1) = 1, level(v2) = 2, level(v3) = 3, level(vt0) = level(vt1) = 4, label(v1) = x1,
label(v2) = x2, and label(v3) = x3.
Given an OBDD (π, G, O), the following two reduction rules can be applied to G = (V, E):
• Type 1: Let v, w ∈ V be two nodes with var(v) = var(w), high(v) = high(w), and low(v) = low(w). Then the reduction can be performed by:
1. redirect all the edges that point to v to the node w, 2. insert w into O if v ∈ O,
3. delete v from V and O, and delete two output edges of v from E.
• Type 2: Let v ∈ V be a non-terminal node with low(v) = high(v). Then
1. redirect all edges that are pointing to v to the node low(v), 2. insert low(v) into O if v ∈ O,
3. delete v from V and O, and delete the two output edges of v from E.
In Figure 2.2 and Figure 2.3 the application of the reduction rules is illustrated. The rule of type 1 guarantees the sharing of isomorphic subgraphs; type 2 removes nodes that have only one child.
An OBDD is called reduced if there is no node where one of the two type of reduction rules can be applied.
In this thesis, only reduced and ordered BDDs are considered. For simplicity, ordered and reduced BDDs are called BDDs.
xi xi
xj xj
xi
xj xj
f f
Figure 2.2. Type 1 reduction rule
xi
xj xj
f f
Figure 2.3. Type 2 reduction rule
2.1.3 SAT Problem
SAT problem appears in many contexts in the field of Computer-Aided Design (CAD) of integrated circuits.
Let B denote the Boolean domain {0, 1}, and Xn := {x0, x1, . . . , xn} be a finite set of Boolean variables. A literal is a Boolean variable xi or a negated Boolean variable xi. A clause ω is the disjunction (OR) of one or more literals. A Conjunctive Normal Form (CNF) formula ϕ is the conjunction (AND) of n clauses ω1, . . . , ωn. A variable whose binary value has already determined is considered to be assigned. A literal xi is said to be satisfied if its variable is assigned to 1; a literal xi is said to be satisfied if its variable is assigned to 0. A clause is said to be satisfied if at least one of its literals is satisfied. An assignment α for a formula ϕ is a set of
assigned variables and their corresponding binary values and denoted as ϕ|α. It will be convenient to represent such assignments as sets of variable and value pairs, for example α ={x1 = 1, x2 = 0, x3 = 1}. Sometimes it is convenient to indicate that a variable x is assigned without specifying its actual value. In such cases, the notation v(x) is used to denote the binary value assigned to x. A satisfying assignment α for a CNF formula ϕ satisfies all clauses of the CNF formula.
A SAT instance is a CNF formula ϕ over n binary variables Xn. The formula ϕ denotes a unique n-variable Boolean function f (x1, . . . , xn). A function f can be represented by many equivalent CNF formulas. Solving the SAT problem is to find a satisfying assignment α for a given formula of the function f (x1, . . . , xn) that makes the function equal to 1 or proving that the function is equal to the constant 0.
Example 2. A given function f = (x1+ x2 + x3)· (x1+ x2+ x3)· (x2+ x3) is just
represented by a CNF formula.
In order to find the satisfying assignment, a backtracking search algorithm is im-plemented by a search process that implicitly traverses the space of 2npossible binary assignments to the problem variables. The SAT problem in general is NP-complete. During the search, a variable is assigned or unassigned with an implicit value of X. An assignment α is complete if |α| = n; otherwise it is partial. Evaluating a formula ϕ for a given truth assignment α yields three possible outcomes:
1. ϕ|α = 1: we say that ϕ is satisfied and refer to α as a satisfying assignment ;
2. ϕ|α = 0: we say that ϕ is unsatisfied and refer to α as an unsatisfying assign-ment ;
This last case can only happen when α is a partial assignment. The unassigned literals of a clause are referred to as free literals. A clause is said to be unit clause if there is only one free literal in the clause.
Formula satisfiability is concerned by determining whether a given formula ϕ is satisfiable and identifying a satisfying assignment for it. Most algorithms for solving the SAT problem of CNF are based on the Davis-Putnam procedure [23] and the Davis-Logemann-Loveland procedure [22]. Starting from an empty assignment, a backtrack search algorithm traverses the space of assignments implicity and organizes the search of a satisfying assignment by maintaining a decision tree. Each node in the decision tree specifies an elective assignment to an unassigned variable; such assignments are referred to as decision assignment . A decision level is associated with each decision assignment to denote its depth in the decision tree; the first decision assignment at the root of the tree is on decision level 1. The search process iterates through the following steps:
1. Extending the current assignment by making a decision assignment to an unas-signed variable. This decision process is the basic mechanism for exploring the new regions of the search space. The search terminates successfully if all clauses become satisfied; it terminates unsuccessfully if some clauses remain unsatisfied and all possible assignments have been exhausted.
2. Extending the current assignment by following the logic consequence of the assignments made thus far. The additional assignment is denoted as implica-tion. The implication process may also lead to the identification of one or more unsatisfied clauses implying that the current assignment is not a satisfying as-signment. Such an occurrence is referred to as a conflict and the associated
unsatisfying assignment is called conflicting assignment.
3. Undoing the current assignment, if it is conflicting, so that another assignment can be tried. This backtracking process is the basic mechanism for retreating from regions of the search space that do not correspond to satisfying assign-ments.
The average complexity of the above search process depends on how decision, im-plication, and backtracking are made, as well as the formula itself. The implications that can can be driven from a given partial assignment depend on the set of available clauses. In general, a formula consisting of more clauses will enable more implications to be derived and will reduce the number of backtracks due to conflicts.
The basic mechanism for deriving implications from a given clause database is Boolean Constraint Propagation (BCP) [37, 58]. Consider a formula ϕ containing the clause ω = (x0+ x1+ x2) and assume x0 = 0, x1 = 1. For any satisfying assignment to ϕ, ω requires that x2 = 0, and we say that x0 = 0, x1 = 1 implies x2 = 0 due to
ω. In general, given a unit clause (l1+ . . . + lk) of ϕ with free literal lj, consistency requires lj = 1 since this represents the only possibility for the clause to be satisfied. If lj = x then x = 0 is required; otherwise x = 1 is required. Such an assignment is referred to as implication and corresponds to the application of the unit clause rule proposed by M. Davis and H. Putnam [23]. BCP refers to the iterated application of this rule to a clause database until the set of unit clauses becomes empty or one or more clauses become unsatisfied. In general, BCP consists of the identification of unit clause and the creation of the associated implications.
Example 3. In order to find out the satisfying assignment for the CNF formula in
1. Making a decision to an unassigned variable. We select x1 and set x1 = 0.
2. No implication can be done. Selecting the unassigned variable e.g. x2 and set
x2 = 0.
3. Because x1 = 0, x2 = 0, in order to satisfy clause (x1 + x2+ x3), x3 = 1 must
be set. It is the implication. But at the same time, another implication from clause (x1+ x2+ x3) lead to x3 = 0. It is a conflict.
4. Undoing the assignment x2 = 0, set x2 = 1. It still leads to a conflict.
5. Undoing the assignment x1 = 0, set x1 = 1. It satisfies the clause (x1+ x2+ x3)
and clause (x1+ x2+ x3).
6. Select the unassigned variable x2 and set x2 = 1. It satisfies the third clause.
7. We found the solution {x1 = 1, x2 = 1, x3 = 0} or {x1 = 1, x2 = 1, x3 = 1}.
2.2
Digital Circuits
2.2.1 Combinational Logic Circuits
The basic building blocks of a computer are called logic gates or just gates. Gates are basic circuits that have at least one (and usually more) input(s) and exactly one output. Input and output values have the logical values true and false. In computer architecture it is common to use 0 for false and 1 for true. Gates have no memory. The value of the output depends only on the current input values. This fact makes it possible to use a truth table to fully describe the behavior of a gate.
We usually consider three basic kinds of gates: AND, OR, and INVERTER. Re-cently, there is a renewed interest in multiplexer based design styles. The typical
S d0 d1
f s
s f(d0) . s f(d1).
Figure 2.4. Multiplexer cell MUX of AND, OR, and INVERTER
d0 d1
s s
f
Figure 2.5. PTL multiplexer as wired OR of two NMOS transistors
multiplexer cell is denoted as MUX, and it is defined by its standard AND-, OR-, INVERTER-based realization (as given in Figure 2.4). The left input s is called con-trol input, the upper inputs d0, d1 are called data inputs (left data input d0= 0-input, right data input d1= 1-input). The multiplexer can be implemented by Pass
Transis-tor Logic (PTL), too. PTL uses only two transisTransis-tor to realize a multiplexer (a wired OR and two NMOS transistors, see Figure 2.5). s is called control input , d0, d1 are called data inputs and f is called data output .
Two types of libraries are typically considered for a combinational logic circuit. One is the library STD, which consists of the 2-input, 1-output AND, OR gates and the 1-input, 1-output inverter NOT. Another one is MUXLIB, which merely consists
x
if
1f
0Map
v
f
x
if
1f
0v
f
1 0 sFigure 2.6. Mapping a BDD to a circuit
of several types of multiplexers with (at most) three inputs and one output.
A combinational logic circuit over a fixed library is modeled as a directed acyclic graph C = (V, E) with some additional properties: each vertex v∈ V is labeled with the name of a basic cell or with the name of a Primary Input (PI) or Primary Output (PO). The collection of basic cells available is given in advance by a fixed library such as STD or MUXLIB. There is an edge (u, v) in E from vertex u to v, if an output pin of the cell associated to u is connected to an input pin of the cell associated to v, i.e. edges contain additional information to specify the pins of the source and sink node they are connected to. Vertices have exactly one incoming edge per input pin. Nodes labeled as PI (PO) have no incoming (outgoing) edges. The size of the circuit |C| is as usually given by |E| + |V |.
2.2.2 BDD Circuits
A combinational circuit implementing a function f can be retrieved from a BDD by replacing each node with a multiplexer (see Figure 2.6).
The BDD circuit [11] of a BDD over the library MUXLIB is now obtained by the following construction: Traverse the BDD in order and replace each non-terminal node v in the BDD by a MUX cell, connect the control input with the PI xi, corresponding
X X X 3 2 1 0 1 (a) MUX MUX MUX 0 1 1 X X X 3 2 1 (b) Figure 2.7. BDD circuit over MUXLIB
to the label of the BDD node. Then, connect the 0-input to low(v), the 1-input to high(v). At the end connect the output of the multiplexer which substitutes the root node with a PO. Figure 2.7 (b) shows the BDD circuit of an example BDD given in Figure 2.7 (a). BDD circuits over the library STD are defined in the following. Take the BDD circuit over MUXLIB and substitute the MUX cells by the standard realization of the MUX cells over STD, the resulting circuit is called the BDD circuit defined over STD. The BDD circuit over STD for the same example BDD is given in Figure 2.8.
Remark 1. As suggested in [11, 10], the MUX cells connected to constant values can
be simplified. But in our approach we do not make use of this, since - as will be shown later - this “destroys” the testability.
2.2.3 Circuits with Tri-state Elements
A circuit with tri-state elements is like an ordinary circuit, except that it has an additional input that we shall call “enable”. When the enable input is 1, the circuit
X X X 3 2 1 0 1 1
Figure 2.8. BDD circuit over STD
behaves exactly like the corresponding normal (not tri-state) circuit. When the enable input is 0, the outputs are completely disconnected from the rest of the circuit, named high impedance state (commonly denoted by Z) [90].
Current industrial circuit designs often contain tri-state (3-states) logic primitives. Tri-state buses and bus drivers, as well as transmission gate logic are commonly found in circuits such as signal- or micro-processors, micro-controllers, and various common peripheral subsystems. Circuits consisting of Boolean as well as tri-state primitives will be called tri-state circuits. In [1], the merits of tri-state logic is summarized as follows: “Tristate logic allows several devices to time-share a common wire, called a bus”. And indeed, this is the one major reason why bus-structured designs are employed. In tri-state circuits, the symbol Z denotes a high impedance state; symbol U (for unknown value) denotes a value that cannot be further determined and which can be any value of 0, 1, and Z. Table 2.1 exemplary shows the truth table of an AND gate in the 4-valued domain: 0,1,U,Z.
Table 2.1. 4-valued AND gate AND 0 1 Z U 0 0 0 0 0 1 0 1 U U Z 0 U U U U 0 U U U D C control data O out if C=1 then O=D if C=0 then O=Z DRIV control(B) data(A) 0 1 Z U 0 Z 0 U U 1 Z 1 U U Z Z U U U U Z U U U
Figure 2.9. Element and truth table of DRIV bus-driver
The main tri-state primitive elements BUS and BUS-driver are defined as follows:
Definition 2.2.1. A BUS-driver is some implementation of a 3-terminal switching
device [90], having a data input that is propagated to the data output in case the control input is at a logic value of 1, in case the control input is at 0, the output is at high impedance, denoted by signal value Z. In detail, if the output value is at high impedance when the control input is 0, the BUS-driver is named DRIV; otherwise the bus-driver is named NDRIV. Figure 2.9 and Figure 2.10 show the truth table of
D C control data O out if C=0 then O=D if C=1 then O=Z NDRIV control data 0 1 Z U 0 0 Z U U 1 1 Z U U Z U Z U U U U Z U U
Table 2.2. Truth table of 3-state BUS BUS data(B) data(A) 0 1 Z U 0 0 U 0 U 1 U 1 1 U Z 0 1 Z U U U U U U
Table 2.3. Truth table of 3-state BUS0
BUS0 data(B) data(A) 0 1 Z U 0 0 U 0 U 1 U 1 1 U Z 0 1 0 U U U U U U
a DRIV and NDRIV bus-driver, respectively. DRIV and NDRIV can not propagate the Z data value. For some types of tri-state drivers, propagation of the Z data value is allowed, which are called (N)SWI in this thesis.
Definition 2.2.2. A bus, at the level of ATPG, is any node driven by more than one
element. Three different types of buses are used. BUS is used to model 3-state buses, BUS0 and BUS1 are used to model 3-state buses with a pull-down or pull-up load, respectively. The truth-table for the bus types are shown in Table 2.2, 2.3, and 2.4.
2.3
Fault Models
Even if circuits are correctly designed, a fraction of them might behave faulty due to physical defects caused by imperfections during the manufacturing process. Fault
Table 2.4. Truth table of 3-state BUS1 BUS1 data(B) data(A) 0 1 Z U 0 0 U 0 U 1 U 1 1 U Z 0 1 1 U U U U U U
models which cover a wide range of the possible defects are defined and tests for faults in the fault models are constructed. We give a short description of the fault models considered in this thesis.
2.3.1 Stuck At Fault Model
A fault in the Stuck At Fault Model (SAFM) [14] causes exactly one input or output pin of a node in the circuit to have a fixed constant value (0 or 1) independently of the values applied to the PIs of the circuit.
The SAFM is basically described by a so called “stuck at 0” (sa0) and a “stuck at 1” (sa1) fault for each connection in the circuit. It is assumed that in the fault-free circuit each connection settles to its calculated faultfree state and the presence of a Stuck At Fault (SAF) will prevent the state. In other words, a SAF will constantly tie the connection to either ‘0’ (in case of a sa0) or to ‘1’ (in case of a sa1). It is further assumed that only one SAF is present and that the fault caused by a defect (e.g. short to ground, or short to Vdd etc.) is constantly present. Such a fault effect can be propagated to any primary output. To detect a SAF only one test vector is needed, i.e. the excitation and propagation can be done by the same test vector. A SAF is considered to be detected if the corresponding net connection can be excited
a b c e f h 0/1 0 0 1 0/1
Figure 2.11. Stuck at fault
(i.e. to ’1’ for a sa0 fault) and the fault effect can be propagated from the fault site to some primary output.
Example 4. Figure 2.11 shows an example of a SAF. At point e there is a sa1 fault.
It means although input b and c have been set to value 0, e still has the value 1. By setting the input a to value 1, this fault effect can be propagated to output h. This SAF can be detected.
2.3.2 Path Delay Fault Model
Whereas the SAFM is a fault model to verify the static behavior of a circuit, the purpose of delay testing is to ascertain that the circuit under test meets its timing specifications. In the Path Delay Fault Model (PDFM) [83, 71] it is checked whether the propagation delays of all paths in a given circuit are less than the system clock interval.
A path π is given by an alternative sequence of nodes and edges (v0, e0, . . . , vn+1, en+1) that starts at a PI v0 and ends at a PO vn+1. Inputs of nodes on the path where no edge ei of the path ends are called off-path inputs.
A transition ( 0 → 1 = rising or 1 → 0 = falling) propagates along π, if a sequence of transitions t0, t1, . . . , tn+1occur at the nodes v0, v1, . . . , vn+1, and ti occurs as a result of ti−1. There is a Path Delay Fault (PDF), if the actual propagation delay
of a (rising or falling) transition along π exceeds the system clock interval.
For the detection of a PDF, a pair of patterns (I1, I2) are required rather than a single pattern as in SAFM: The initialization vector I1 is applied and all signals of the circuit are allowed to stabilize; then the propagation vector I2 is applied and after the system clock interval the outputs of C are controlled.
Definition 2.3.1. A two-pattern test is called a robust test for a path delay fault
(RPDF test), if it detects that fault independently of all other delays in the circuit and all other delay faults that are not located on this path.
It turns out that for the circuits considered in this thesis the construction of tests with the following (even stronger) property is possible: For each PDF there exists a robust test pattern (I1, I2) that sets all off-path inputs to non-controlling values1 on application of I1and remains stable during application of I2, i.e. the values on the off-path inputs are not invalidated by hazards or races. Robust tests with the properties mentioned above are also called strong RPDF tests. In this thesis, we only use such tests, but for simplicity we call them RPDF tests, too. For a detailed classification of PDFs refer to [65].
2.3.3 Bridging Fault Model
Bridging Faults (BFs) [59] are caused by shorts between normally unconnected signal lines [2]. Since the lines involved in a short become equipotential, all of them have the same logic value. For a short line g, we distinguish between the value one could actually observe and the value of g as determined by its source element; the
1A controlling value at the input of a node is the value that completely determines the value at the output, e.g. 1 (0) is the controlling value for OR (AND) and 0 (1) is the non-controlling value for OR (AND).
g h BF g h Z(g,h)
Figure 2.12. Bridging fault
latter is called driven value. Figure 2.12 shows a general model of a BF between two lines g and h. Z(g, h) is the function introduced by the BF and has the property Z(g, h) = g. The fan-out of Z is the union of the fan-outs of the shorted signals. Note that the values of g and h in this model are their driven values, but these are not observable in the circuit.
When the two shorted lines have opposite driven values, one value (the strong one) overrides the other. If 0 is the strong value, then Z(0, 1) = 0, and the function introduced by the BF is AND. The fault is named AND BF. In this thesis we consider only AND BFs. The results for OR BFs (the strong value is 1) can be obtained by similar argumentation.
Considering a gate level description of a design, one can distinguish between single BFs and multiple BFs (SBF and MBF) which connect two lines and more than two lines, respectively. In this model an MBF can be seen as several SBFs with common lines. As shown in [59], MBFs are often detected by tests for SBF that are part of the MBF, therefore in this thesis only SBFs are considered.
circuit
fault list
detected
faults untestablefaults
ATPG test set
Figure 2.13. Main inputs and outputs of the ATPG process
2.4
ATPG
In order to test physical defects of a circuit that are caused by imperfections during the manufacturing process, there is a particular step in the design flow: the post-production test. In practice the post-post-production test is carried out by applying input stimuli - so called test patterns - to the circuit and controlling the output response with respect to its correctness. Automatic Test Pattern Generation (ATPG) is the process of generating a set of test patterns for a circuit with a given list of considered faults. An abstract representation of the main inputs and outputs of the ATPG process is shown in Figure 2.13: Inputs are the circuit description, and a list of faults still to be processed (derived from the circuit description and the considered fault models). Outputs are a list of test patterns, called the test set , and lists of detected and proven untestable faults. Each time when a fault has been found detected or untestable, it is removed from the fault list. Each time when a test pattern has been generated, it is added to the test set. The remainder of this section introduces the main components of ATPG.
2.4.1 Deterministic Test Generation
The basic problem in ATPG is Test (Pattern) Generation (TPG or TG) that is fault-oriented and deterministic. Since the early 1960s, considerable research efforts have been spent on the problem of test generation. Initially, algebraic methods, ma-nipulating Boolean expressions of circuits, were used, such as [64] and [74]. But these methods have been found to require large quantities of time and memory. The test generation methods that work with topological gate-level descriptions of circuits have been found to be successful. Those traditional “path-searching” algorithms ap-ply branch and bound techniques to implicitly enumerate the solution search-space (all possible input vectors to a circuit). A formalization of the Single Path Sensiti-zation (SPS) method [6], the D-algorithm [68], was the first algorithm to guarantee complete test generation, that is: If a test for a given fault exists, a test is found; failure to find a test implies that the fault is untestable. Two algorithms developed later, in addition to the D-algorithm, constitute the basis of most general test algo-rithms: the PODEM-algorithm [38] and the FAN-algorithm [36]. The general form of these algorithms, which have to search a large search-space, consists of a loop over two steps:
1. Implication of mandatory assignments
2. Heuristic choice
Mandatory assignments are those assignments that have to be made to solve a given problem. For example, in Figure 2.14, in order to activate the SA1 fault, the signal value of both b and c must be assigned to “0”, which is the only way to drive the OR gate’s output to the value opposite to the stuck at level. Ideally, maximal implication
a b c d e f g h j sa1 0/1 0 0 1 0/1 i k l
Figure 2.14. Example circuit with a SA1 fault and a test for it
is performed. However, in practice, in large circuits, it is time-consuming to identify all mandatory assignments, thus only those that can be found by techniques with low time-complexity are really implied. If no more implications can be performed, and a solution has still not been found, some choice will have to be made (Step 2). In Figure 2.14, after the fault has been activated, it must be chosen through which AND gate to propagate the fault-effect. Here both possible choices lead to a solution. In general, solving one or more line-justification problems may lead to conflicting assignments. Therefore, it is necessary to keep track of the decisions made during the heuristic choices. In case of a conflict, the process falls back to the last made decision, if there are alternative choices, the other decision is made, otherwise it is discarded and the process falls back to the previous last made decision. This process of systematically making another decisions is called backtracking and it commonly found in many similar search algorithms. If backtracking occurs and no more decisions can be made, there is no solution in the search-space, i.e. the fault is untestable.
The FAN-algorithm identifies more implications while searching for a test, hence playing less on heuristics, and therefore it is superior in performance to the PODEM and D-argorithm. Additional techniques, such as “dominators” and (static and dy-namic) [44, 70] “learning by contraposition” [73], and ”recursive learning” [49], are used to identify more implications.
2.4.2 Fault Simulation
In order to reduce the number of faults for which the NP-complete fault-oriented deterministic TPG processes have to be applied, and also to reduce the number of test patterns in the final test set, normally TPG is combined with fault collapsing and Fault Simulation (FS). Fault collapsing is a preprocess which makes sure that from a group of equivalent faults only one is present in the initial fault list. A FS algorithm determines which (remaining) faults are detectable by a given test pattern. In general each test pattern generated by TPG may detect more faults than just the one for which it has been created. An FS algorithm is used to identify the additionally detected faults. After a test pattern has been generated for one fault, the remaining unspecified inputs of the test pattern are specified by random padding to increase the potential coverage of the test. Thereafter, FS is applied to remove all detected faults from the fault list; this is called fault dropping. Such a combination of TPG and FS constitutes a single ATPG stage: a stage of an ATPG system. The ATPG systems introduced in [73, 91] incorporate fast fault simulation algorithms [4, 5, 55, 72, 88]. These algorithms exploit circuit structure characteristics (fanout free regions, dominators, independent branches) to minimize the amount of explicit fault simulation. They often exploit the bitwise parallel computer operations by
Initialize fault list Fault-collapsing Learning Other preprocesses Random TPG Parallel Patterns FS still useful? stop or no fault left? Deterministic TPG test? Single pattern FS Y N N N Y Further ATPG stages Test Set Compaction, Other postprocesses Y
Figure 2.15. General structure of the state-of-the-art of ATPG systems
packing multiple logic values into computer words and carrying out logic evaluations for multiple patterns in parallel (parallel patterns FS).
2.4.3 ATPG Systems
A complete industrial ATPG system used at Philips Semiconductors GmbH, has the basic structure shown in Figure 2.15 [90]: It starts with preprocessors, among which there are fault collapsing and static learning. Next, a random TPG stage (random TPG and parallel pattern FS), limited by certain stop-criteria, generates tests for the easy-to-detect faults, commonly using parallel patterns FS for efficiency. Thereafter, one or more deterministic ATPG stages try to find tests for the remaining faults. Each next stage has a higher capacity to identify implications. Each deterministic ATPG stage consists of a deterministic TPG and a (single pattern) FS algorithm. Stop-criteria, per fault but also possibly per stage, determine when to stop TPG, or the entire ATPG stage. Finally, test set compaction is applied.
Random TPG is normally used as the first TPG stage. Random input patterns are evaluated by FS, and detected faults are removed from the fault list. Patterns that detect no additional faults are discarded. As there are many faults that are “easily” testable, i.e. there are many possible input patterns that constitute a test for such faults, random TPG may reach reasonable fault coverage. The result depends on the fraction of “easy” faults in a circuit, and the speed of FS (which depends on the FS algorithm and the circuit size). Especially during random TPG, parallel patterns FS can be exploited beneficially. Usually, the more random patterns have been fault simulated, the fewer new faults will be found to be detectable with each successive pattern. If random TPG is carried out too long, many test patterns will be added that detect only a few faults, resulting in a large test set. In addition, if many patterns are fruitlessly tried by FS, before finding a new useful pattern, the advantage of random TPG (speed) has disappeared. Therefore random TPG is constrained, as a simple example, by stopping after a certain number of useless patterns.
In the second and later stages the remaining faults are targeted. As described earlier, these stages consist of a deterministic TPG algorithm, combined with a single pattern FS algorithm. As deterministic TPG is NP-complete, that is, in the worst-case it may have to search through the entire search-space that is exponential in the number of inputs to the circuits. In practice a deterministic TPG can be constrained. Simple constraints can be a prefixed limit to the number of backtracks that may be performed per fault, or a limit to the amount of time to be spent per fault. Thus, in addition to Figure 2.13, a list of aborted faults would normally exist, to which ATPG could not find a solution due to the constraints.
test set size without compromising fault coverage. The commonly used technique is reverse fault simulation: All detected faults are again marked undetected, test patterns are faults simulated in the reverse order in which they were generated in. Test patterns that were generated late in the ATPG process can often detect some faults that were already marked detected by earlier patterns. That is why the combined coverage of several “late” patterns can make earlier patterns unnecessary. Reverse fault simulation can also profit from parallel pattern FS.
Testing of BDD Circuits
In this chapter, the testability of BDD circuits under the SAFM, the PDFM, and the BFM is introduced. It is proven that test patterns under those fault models can be generated in polynomial time [77, 78, 81]. A new technique that adds one new input and one inverter to the BDD circuit is proposed. Using this technique, the testability of circuits under the SAFM, the PDFM and the BFM can be greatly improved. Especially, under SAFM and PDFM, 100% testable circuits can be generated [27, 28, 78]. Through sifting the order of the BDD variables, the BDD can be optimized. This chapter also shows the changing testability of BDD circuits by optimization of BDDs [34, 76].
3.1
Introduction
Since BDDs have been proposed in [52, 3] several applications have been studied, where this data structure can be successfully applied. In formal verification BDDs have become the state-of-the-art for function representation and manipulation (see e.g. [18]). BDDs have also been studied in the field of logic synthesis, since they allow to combine aspects of circuit synthesis and technology mapping [41]. BDD circuits can
be easily realized by replacing each non-terminal node with a MUX cell. And recently, there is a renewed interest in multiplexer based design styles, since multiplexer nodes can often be realized at very low cost, e.g. in Pass Transistor Logic (PTL). In addition, these techniques allow to consider layout aspects during the synthesis step and this guarantees high design quality [19, 32, 63, 56].
One of the most important aspect during circuit design is the testability of the circuit. Multiplexer based BDD circuits have been studied intensively under various fault models [9, 8, 11, 10]. (For an overview see [12].) BDD circuits have good testability under the SAFM and the PDFM. But no approaches has been proposed to guarantee 100% testability in a “systematic way”. For example, [11] presents an algorithm that can compute all redundancies of the circuit in polynomial time. But the removal of these redundancies can generate new ones (so-called 2nd-generation redundancies).
In order to test a circuit, we put a set of test patterns to the inputs of the circuit and compare the current outputs of the circuit with the correct outputs. Test Pattern Generation (TPG) has been proven to be NP-complete [90]. But for BDD circuits TPG can be carried out in polynomial time.
In this chapter, a simple transformation that adds only one extra input and one inverter is presented to guarantee full testability of a circuit derived from a BDD description under the SAFM and the robust PDFM. The resulting circuits are free of redundancies. The algorithm has been implemented as a tool for Multiplexor Transformation for Testabilty (MuTaTe). Experimental results are given that show the advantages of the approach compared to traditional synthesis approaches and to “classical” mapping of BDDs.
Although the SAFM and the PDFM are the standard fault models, the frequently occurring faults in practice are unintentional shorts, denoted as bridging faults [7, 31]. So an increasing attention has been given to the area of modeling and testing of bridging faults [89, 54].
In this chapter, bridging fault testability is also analyzed. For circuits derived from BDDs the complete test pattern generation process for bridging faults is formulated in terms of symbolic BDD manipulations. These symbolic operations allow to consider all possible test patterns at the same time. This can be beneficial for compaction of a test pattern set.
The size of the circuit is directly proportional to the given BDD size. So all BDD optimizations based on variable ordering directly transfer to the resulting circuit sizes. At the same time, the change of variable ordering can optimize the testability of BDD circuits. Experimental results show the influences of variable ordering on the testability of BDD circuits.
3.2
ATPG in Polynomial Time
A BDD circuit still has the BDD structure, so test pattern generation for BDD circuits can use the BDD operations. Then TPG can be carried out in polynomial time.
3.2.1 BDD Circuits of General Boolean Functions
For test pattern generation some functions are useful. They are defined as follows:
Definition 3.2.1. Function fdetect denotes the conditions of the fault’s activation. E.g. for a sa0 at a line l, fdetect is f (l) = 1.
Table 3.1. Detect function for SAF
line fault detect function fdetect
s sa0/1 f (d0)· f(d1)
s sa0/1 f (d0)· f(d1)
s· f(d1) sa0/1 f (d0)· f(d1)
s· f(d0) sa0/1 f (d0)· f(d1)
Definition 3.2.2. Function fdetect(g, h) denotes the conditions of setting line g to the value 0 and h to the value 1 at the same time in the circuit without fault. Note, that fdetect(g, h)= fdetect(h, g).
Definition 3.2.3. The necessary condition to propagate the value of a line g to a
primary output o is denoted by function fpropagate
o (g).
Theorem 1. Let C be a BDD circuit. The test pattern generation of C under the
SAFM can be carried out in polynomial time.
Proof. Let v be any multiplexer node in the BDD circuit C.
In order to detect a fault of the SAFM inside the node v, we should apply a data input value 00, 01, 10, or 11 at the node v to detect the fault. For the multiplexer shown in Figure 2.4, there are four internal lines: s, s, s· f(d1), s· f(d0). Table 3.1 shows the function fdetect that should be set to active the faults at those lines. Then propagate the difference of the node’s output to a primary output.
The test pattern can be generated as follows:
1. Determine the Inputs to active the SAF: For each SAF, Compute the BDDs of responded detect functions as shown in Table 3.1. Because the BDD cor-responding to C is ordered and reduced, so the time complexity of operation Apply is O(|C| · |C|) [17]. So the detect functions can be calculated in time
O(|C|2). Then Solve the satisfiability problem for the resulting BDDs. E.g.
f (d0)·f(d1) is satisfiable, if 01 is applicable to the data inputs of v. This can be done in linear time because it is necessary to find only one path to the terminal node ‘1’ and the variables are encountered at most once. Those encountered variables are determined at the same time.
So in computational time O(|C|3), applicable data inputs of the node v can be determined. If it is applicable, the primary inputs of the circuit C which generate the corresponding data inputs are determined at the same time.
2. Determine the Inputs to propagete the SAF: The difference of the node’s output can be propagated to a primary output by setting the control inputs on a path from v to the primary output. Because these control inputs have not been set to generate the corresponding data inputs of v due to the ordering of the BDD and can be set exactly once on the path.
So a test pattern for a fault under the SAFM in the node v can be generated in time O(|C|3) if the needed data input value of v is applicable.
For the SAF at outside of the multiplexer:
1. The fault at select line S can be detected same as the line s inside the multi-plexer.
2. In order to detect a SAF at the output of the node v, we need set f (v) = 0 for sa1 or f (v) = 1 for sa0 and propagate the difference to a primary output. It is easy to see that the time complexity is O(|C|)
multiplexer or terminal. So the test pattern generation can be done in time O(|C|).
So the test pattern of the faults inside and outside the multiplexer can be generated in polynomial time.
Theorem 2. Let C be a BDD circuit. The test pattern generation of C for the PDFM
can be carried out in polynomial time.
Sketch of proof. Any path from a primary input to a primary output consists of mul-tiplexers. At each node the propagated path is selected by a primary input. Due to the read-once property of BDDs each primary input only influences one node on a path. Therefore, propagation through multiplexers can be determined in linear time. Now, consider an arbitrary multiplexer node internal in the circuit. At the data inputs (d0, d1), there are two pairs of input values: i.e. p0 = (0, 1) and p1 = (1, 0). Four paths from inputs to outputs have to be tested: one path from each input d0 and d1, and two paths from the select input s. In order to test the path along d0 with respect to a rising transition, s should be set to 0, p0 should be set to the date inputs (d0, d1) at first, at second time, p1 should be set. The falling transition and testing
d1 are similar cases. Testing the non-inverted path starting at s is done by applying
p0 and switching s, the inverted path is tested by applying p1.
As explained above, the set of the applicable pairs p0 and p1 can be determined in polynomial time.
So test pattern for a fault under the PDFM can be generated in polynomial time if the needed input values at the date input of the corresponding node is applicable.
Theorem 3. Let C be a BDD circuit over MUXLIB or STD. The test pattern
