E0C37120
Multifunction Buffer IC
■ DESCRIPTION
The E0C37120 is a multifunction buffer IC suitable for use as a PCMCIA interface buffer and 3.3V↔5V conver- sion level shifter. Because it enables a multi-chip buffer IC to be integrated into a single chip, this product helps you miniaturize your system.
The E0C37120 is designed to be particularly effective when it is used with the E0C37109 (MPU), SEIKO EPSON 32-bit single-chip RISC microcomputer. When used in this way, it provides superior characteristics as an interface buffer for PCMCIA cards capable of hot insertion/removal.
■ FEATURES
• Incorporates 26-bit mono-directional buffer
• Incorporates 16-bit bi-directional buffer
• Power supply on target side: 3.3V, 5V, power-off
• Incorporates 3.3V/ 5V level shifter
• High-speed 0.35- µ m CMOS process
• Compact package: QFP15-100pin
■ BLOCK DIAGRAM
3.3V 3.3V/5V/Off
Vss
3.3V/5V/Off
SA0–19 TA0–19
TA20–25 AEN#
SA20–25
TEST
SD0–15 TD0–15
DEN#
DDIR
SVcc Vss SA0–19 EN#
SA20–25
EN#
DIR
TVcc
TA0–19
TA20–25
SVcc Vss SD0–15
EN#
DIR
Address Bus Buffer E0C37120
Data Bus Buffer Test Logic Circuit
TVcc
TD0–15
∗ The pin names with the suffix # are those of active-low pins.
■ PIN DESCRIPTION
● Pin Assignment
● Pin Function
Note: Symbols representing the type of pins mean the following.
I: Input port, O: Output port, I/O: Bi-directional port, P: Power port, PD: with pull-down resistance
Pin name SA0–19 SA20–25
SD0–15 TA0–25 TD0–15 AEN#
TEST DEN#
DDIR
SVcc TVcc
Vss
Description Address bus signal on system side
Address bus signal on system side
When TEST = high, the pins SA20–25 function as test-signal output pins. When these pins are not used, connect them to Vss via a resistor of 10 kΩ or more.
Data bus signal on system side
When these pins are not used, connect them to Vss via a resistor of 10 kΩ or more.
Address bus signal on target side Data bus signal on target side
When these pins are not used, leave them unconnected.
Address bus buffer-enable signal Test signal
Always connect this pin to Vss.
Data bus buffer-enable signal Data bus buffer-direction signal
When DDIR = high, this signal is driven in the direction SDxx ← TDxx. When DDIR = low, this signal is driven in the direction SDxx → TDxx.
Power supply on system side and for internal logic (3.3 V) Make sure power is fed to all the SVcc pins.
Power supply for address bus buffer and data bus buffer on system side (3.3 V/5 V/Off) When turning the power off, set AEN# high to prevent static current consumption from increasing. Make sure power is fed to all the TVcc pins.
Ground
Be sure to connect all the Vss pins to ground.
Type I I/O
I/O O I/O PD
I I I I
P P
P
No. of pins 20
6
16 26 16 1 1 1 1
2 4
6
Power SVcc SVcc
SVcc TVcc TVcc SVcc SVcc SVcc SVcc
– –
– 50
49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 TA1
TA0 TD0 TD1 TD2 TD3 Vss TVcc TD4 TD5 TD6 TD7 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 SA0 SA1 SA2 SA3 Vss
76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
TA23 TA24 TA25 TD15 TD14 TD13 Vss TVcc TD12 TD11 TD10 TD9 TD8 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA25 SA24 SA23 Vss
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TA2 TA3 TA4 TA5 Vss TVcc TA6 TA7 TA8 TA9 TA10 TA11 TA12 TA13 TA14 TA15 TA16 TA17 TA18 TVcc Vss TA19 TA20 TA21 TA22
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
SVcc SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 DDIR DEN# AEN# TEST SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SVcc
E0C37120
■ ELECTRICAL CHARACTERISTICS
● Absolute Maximum Ratings
Rating Supply voltage Input voltage Output current/pin Total output current Storage temperature
(VSS=0V) Symbol
SVcc TVcc Vpin Iout ΣIout Tstg
Value -0.3 to 4.6 -0.3 to 6.0 -0.3 to SVcc + 0.5 -0.3 to TVcc + 0.5
±30±5 -65 to 150
Note Unit
V V V mA mA
°C
● Recommended Operating Conditions
Condition SVcc supply voltage TVcc supply voltage SVcc pin voltage TVcc pin voltage Operating temperature
∗1
(VSS=0V) Symbol
SVcc TVcc Vpin Vpin Ta
Min.
3.0 3.0 Vss Vss -40
Typ.
3.3 – – – –
Max.
3.6 5.5 SVcc TVcc 85
Note
∗1 Unit
V V V V
°C Power Off (Hi-Z) input is allowed.
● DC Characteristics
Characteristic
High level output voltage (1) IOH =-2mA Low level output voltage (1) IOL=2mA High level input voltage (1)
Low level input voltage (1)
∗1
∗2
(SVcc=3.3V±0.3V, Vss=0V, Ta=-40 to 85°C) Symbol
VOH1
VOL1
VIH1
VIL1
Min.
SVcc - 0.4 – 2.0
–
Typ.
– – – –
Max.
– 0.4
– 0.8
Note
∗1∗1
∗2∗2 Unit
V V V V Pins SD0–SD15
Pins SA0–SA25, SD0–SD15, AEN#, DEN#, DDIR
Characteristic
High level output voltage (2) IOH =-2mA Low level output voltage (2) IOL=2mA High level input voltage (2)
Low level input voltage (2) Pull-down resistance (1)
∗1
∗2
(TVcc=3.3V±0.3V, Vss=0V, Ta=-40 to 85°C) Symbol
VOH2
VOL2
VIH2
VIL2
RPU1
Min.
TVcc - 0.4 – 2.0
– 40
Typ.
– – – – 100
Max.
– 0.4
– 0.8 240
Note
∗1
∗1
∗2
∗2
∗2 Unit
V V V V kΩ Pins TA0–TA25, TD0–TD15
Pins TD0–TD15
Characteristic
High level output voltage (3) IOH =-3mA Low level output voltage (3) IOL=3mA High level input voltage (3)
Low level input voltage (3) Pull-down resistance (2)
∗1∗2
(TVcc=5.0V±0.5V, Vss=0V, Ta=-40 to 85°C) Symbol
VOH3
VOL3
VIH3
VIL3
RPU2
Min.
TVcc - 0.4 – 3.5
– 30
Typ.
– – – – 60
Max.
– 0.4
– 1.0 144
Note
∗1∗1
∗2∗2
∗2 Unit
V V V V kΩ Pins TA0–TA25, TD0–TD15
Pins TD0–TD15
Characteristic Input leakage current Output leakage current Pin capacitance
f=1MHz, SVcc=0V, TVcc=0V Static current consumption
(SVcc=3.3V±0.3V, TVcc=5.0V±0.5V, Vss=0V, Ta=-40 to 85°C) Symbol
ILI
IOZ
CIO
ICCS
Min.
-1 -1 – –
Typ.
– – – 0.3
Max.
1 1 10 35
Note Unit
µA µA pF µA
● AC Characteristics
Characteristic Signal access time Output signal on/off time
(SVcc=3.3V±0.3V, TVcc=5.0V±0.5V, Vss=0V, CL=30pF, Ta=-40 to 85°C) Symbol
tAC
tOZ
Min.
– –
Typ.
– –
Max.
20 20
Note Unit
nS nS
SAxx, SDxx
TAxx, TDxx
TDxx
SDxx
AEN#, DEN#
TAxx, SDxx
tAC tAC
tAC tAC
tOZ tOZ
■ PACKAGE DIMENSIONS
14±0.1 16±0.4
51 75
14±0.1 16±0.4
26 50
INDEX
0.18 25 1
100 76
1.4±0.10.1
1.7max
1 0.5±0.2
0° 10° 0.125 0.5 +0.1–0.05
+0.05 –0.025
(Unit: mm)
QFP15-100pin
■ APPLICATION EXAMPLE
● PCMCIA Buffer
● Level Shifter Buffer
Vcc CA25–22 A21–0 D15–0
ISAENA#
RD/WR#
E0C37120 E0C37109
TVcc
TA25–0
TD15–0 SVcc
SA25–0
SD15–0
DEN#
DDIR AEN#
TEST 3.3V
Address bus Address bus
Data bus Data bus
ISA 5V IC 5V
Vcc CA25–22 A21–0 D15–0
ADATAENA#
RD/WR#
AADRENA#
ACE1#, ACE2#
AOE#
AWE#
AIORD#
AIOWR#
AREG#
ARDY_IREQ#
AWAIT#
ACD1#, ACD2#
AWP_IOIS16#
ARESET ABVD1_STSCHG#
ABVD2_SPKR AVS1, AVS2 AVPPVCC
AVPPPGM AVCC3#
AVCC5#
SLOTA_Vcc
SLOTA_Vcc VPP
Power IC
E0C37109
E0C37120
PCMCIA SLOT TVcc
TA25–0
TD15–0 SVcc
SA25–0
SD15–0
DEN#
DDIR AEN#
TEST 3.3V
Address bus Control signals
Address bus
Data bus
Control signals
Data bus
12V 3.3V 5V
NOTICE:
No part of this material may be reproduced or duplicated in any form or by any means without the written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies contained in this material or due to its application or use in any product or circuit and, further, there is no representation that this material is applicable to products requiring high level reliability, such as, medical products. Moreover, no license to any intellectual property rights is granted by implication or otherwise, and there is no representation or warranty that anything made in accordance with this material will be free from any patent or copyright infringement of a third party. This material or portions thereof may contain technology or the subject relating to strategic products under the control of the Foreign Exchange and Foreign Trade Control Law of Japan and may require an export license from the Ministry of International Trade and Industry or other approval from another government agency.
© Seiko Epson Corporation 1999 All right reserved.
SEIKO EPSON CORPORATION
ELECTRONIC DEVICES MARKETING DIVISION IC Marketing & Engineering Group
ED International Marketing Department I (Europe & U.S.A.) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
Phone : 042-587-5812 FAX : 042-587-5564 ED International Marketing Department II (Asia) 421-8, Hino, Hino-shi, Tokyo 191-8501, JAPAN
http://www.epson.co.jp
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