isi is

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I RUG S I

l _ _ _ _ _ _ _ _ J

Brown University Graphics Systew

LEVELO Extended Machine'

~ussell H. Burns

The Brown University Graphics Project Division of Applied Mathematics

Box F

BI:cwn University

providence, Rhode Island 02912 Septembe!: 15, 1976

'This research is being supported by the National Science Poundation Grant GJ-28401X, the Office of Naval Research, Contract N00014-67-A-0191-0023, and the Brown University Division

of Applied Mathematics; principal Investigator Andries van Dam.

LEVELO is the nucleus program of the BUGS extended machine. This document describes the logic and organization of L.EVELO. I t is intended for use by systems programmers debugging alld modifying the operating s ystem as a guide to the code. A thorough knowledge of the !'lETA 4A Principles of Operation and the LEVELO Extended !'lachine principles of Operation is assumed.

r.

1 Introduction.

...

^,.

... .

^{.. .... 1}

2 The 2. 1

2. 2

S upe ['vi sor . . . .

..

Dispatc her . . . • . •

· .

^•

Program Checks ••••••••••••••••

2.3 Extended Instructions •••••••••

•

•

· .

.. .. . ^{.. .. ..} · ... .

^{• .... 2}

.... .. ...

.. .... 2

...

^{.. .... 2}

...

• ³ .. .. .. .. .. .. .. .. .. .. .. 3 .. .... ... 3 .4 2.3. 1 Execution Contrel Instructions.

2.3.1.1 SIGNAL! The Schedulec •••••••

2.3. 1.2 \;AIT: Suspend Execution ••

2.3. 1.3 POST: Continue Execution.

. .

^{.. .... 5}

• •• 5

3

2.3.1. 4 2 • .1 1.5

ENT: Subroutine RET: Subroutine

En try ••

Exi t.

..

~lanagement . . . . • • • 2.3.2 Data

2.3.2.1 2.3.2.2 2.3.2.3

GET: Get Controlled Storage.

GETMAX: Get Maximum Centrolled FRtE: Free Controlled Storage.

2.3.3 Interprocessor 2.3.3.1 INTB:

Communications •••

Interrupt ME1A 4B ••••

Conteol Blocks •.••••.•

2.4

2.4. 1 Stack Frame Header.

2. 4. 2 2.4.3 CPU

Stack Frame ••••••

Unit Control 2.4.3. 1 A -CP U ... .

· ... .

Blocks.

.. . . .. . .

· ... .

3. 1

1/0 Supervisor" ••••

Reg ister Usage.

3.2 Dispa tcher •••••

· ... . . . . . .

• • •

· ...

3.2. 1 EXCP Routines.

.1.2. 1 1 COMSIO •••••

3.2. 1.2 COMRDY •••••••••••

3.2.2 3.2. 3 3. )

InterJ:upt Routines .•....••••

META 4B Interrupt Processing.

EXCP Processin~ •••

3.4

crc

Processing ••• •

. . _· .

3.4. 1 Unit Dependent Routines •••

3.S _3.6 Timer Control 1/0 Interrupt . . . P.rocessing .... .

· .

3.6. 1 Tin"~r

3.6.2

Interrupt Rontine •••

QTIMER Instruction •• • 3. 6. 3 UPTIl1 Ell lloutine ••

3.7 Control 3.7. 1 Unit

Block s ... ..

Control Block..

BUGSUCB Hacro ••••

•

3.7. 1.1

3.7.1.2 Timer UCH r:xtension ••

.. ..

..

..

· .

•

•

•

· .

· ^.

•

. ..

.. .. .. .. ^.. .. .. .. .. .. .. .. .. ...

.. .... 6

..

^.. ... 7

· .

^.7

Storage. • .. .. .. .. .. .. .. .. .. 8

•

. . .

• •

•

· .

·

•

.. ^. .

•

· ..

.. ...

... 9

.. ^{.. ...}

• •

.. ..

..

..

..

· .

· ..

...

...

.. ... ..

•

.. .. .. .. .. .. .. .... .. .. a ....

...

•

.. ... ..

..

... ..

...

· . ..

...

...

· . . _.. ... ..

· .. ^.. ... ..

10 10 10 10 12 13 13

14 14 14 15 15 15 16 16 17 17 18 18 19 19 19 20 21 21 22

.. .. ....

.. .. .. .. • .. .. .. .. .. 23

The standard LEVELO module i s assembled from t wo SYSIN files, LEVOSUP [CSECT L£1I8LO , entry points L8VELO, DISPATCH, SIGNI\LEV l and LEII010S [CSECT EXCP, entry points EXep, ZLIOH,

UPTIMER, QTJ.MER, and the Unit Control Blocks ]. Functions of the extended machine are roughly dive ided into supervisor functions , i n LEITOSUP, and I /O supervisor fu nctions, in L8V010S. Both source files r eside on the Graphics archival disk, and the text in BUGSLIB TXTL1B on RWB.

The upgraded. L8VO- 2 all

f u nc tion s

version of LEVELO Ear the Null B is no longer being It consists of one CSECT in two SYSIN files, L8VO- 1 and the Graphics archival disk. I\lthough the supervisor are largely the same, the I/O s upervisor has been extens ively re-written in the process of deleting the Null 8 support.

The differellces in t he L8VELO for Dynamic Relocation of Programs and Data will be di~cussed i n another document2

The LEVIlLO s uper:visor handles user requests for execution contr:ol and cor:e management. I t is e nter:ed upon pr:ogram checks a nd super:visor call interr:upts. The s uper:visor oper:ates in s upervisor: mode, with I/O interrupts disabled. Global register

usage is as follo\o1s :

R12 --) usee's stack fr:ame header:

R15 --) user's cur:rent save area

Supe rvisor cal ls are merely reflected up to LEVEL1 by si gnalling the appropriate event name.

lll!!.n:.i. DISPATCH

LEVRLO Dis patch is a simple priorit y dispatcher, enter:ed only whe n a return t o a user would be inadvisable , o.r: ~lhen a nEW task is contending for tile CPU. It searches t he s tack fr:ame queue for the highest pri oLitv s tack f.rame vhich is not i n a wait s ta te , and dispatches it. If all stack frames are in wai t state (MSR bit 6 on), Dispa tch calls UPTIMER3 to compute the running CPU time and t en dispatches the top s tack fra me , placing the machine in a wait state.

&l!j;];.E P GM C IlK

The user: communicates his retjuests for LEVELO services through extended inst ruct ions, which cause operation exceptions . The LEVELO program check handler reflects all other program checks up to LEVEL ·' by signalling the appropriate eV<lnt name (X'llOXx').

3 .Yi<l~ Timer: Centrol, Section 3.6

• If ti,e reason fOL entry was an operati.on exception, the program check l,andler searches for the offending opcode in the extended opcode table. Upon snccess, the program check handler calls the associated routine vi~ H13, and then returns to the user, Ilnless the routine exits to the dispatcher.

• Otherwise, an invalid opcode event is s ignalled up to LEVELl.

The Extended Instruction Handlers are e nter2d either through the progra m check hanrHer or t hrou gh inter na 1 ca 11.

Both the internal calling sequence and the e xtended instruction format will both be described wher.e appropriate.

2.3. 1 EXECUTION CONTROL INSTRUCTIONS

The Execution Ceutrol scheduling, blocking, creation BU GS. A s s u c h, the y a x:e dispatcher and to each othe.r.

I nstructions proviJe the and destruction of tasks in intimately related t~ the

lln t.!:y ... S IG N AL EV

R8 con tains event narue R9 --) sta tus info.x:ma tion

Rl0 contains length of status information

r

---r---r----r---y----r- ^---,

"FC I 00 I En I On I Bs I Os I

L - _ _ _ _ _ _ - i _________ ^~_~ ____________ ^~~ ____________ J

a 8 16 20 32 36 47

The SIGNAL routine acts as the scheduler of interrupt processing. I t searches the appropriate event l i s t for a matching entcy. If none is found, the low o[-der hex digits of the event name a'ca successively ze roed and the list re-seacched. If no entry rna'tches even purtially, the trap event e nt,ry is chosen.

in any case, there ace three possibilities of event list entcy types which could be selEcted:

• If the entry indicates the event should be ignored, SIGNAL exi ts to the Dispatcher.

• If the entry indicates the Event sould be

handled syncronously (immediate event), SIGNAL exits to EN7 processing to start the routine running immediately.

• otherwise SIGNAL creates a new stack frame

header, copying the entry point,priocity, and stack frame size from the event entry and exi ts to the Dispatcher •

.---.----~---T----T---,

I 7E I 00 I X w I Bw I Ow I

'--_______ ..L-___ ..L ____ ...L ___ --1. _____________ .J

o 8 12 16 20 31

The iAIT extended instruction checks the high orde r bit of the I-jait Control Halfword:

• If the bit is on, \,AI T returns to the call ec. (vi a R 13) •

• if the bit is off, WAIT stores the caller's

stack frame address in the WCR, sets the wait bit on in the stack frame MSR, and exits to the dispa tcher.

!lulu.;.

POST

r---T---r----r---r----r---, I FE I 00 I Be I On I Bw I D. I

L -_ _ _ _ _ _ _ ^~ _ _ _ _ _ _ _ _ _ i -___ ~ ___________ _ i _ _ _ ~ _ _ _ _ _ _ _ _ _ _ _ _ J

o 8 16 20 32 36 47

The PQST extended instruction swaps the former contents of the WCH wit h the re turn code: i t then checks the f ormer contents of the WCH:

• If the former: contents were zero, POST returns to the caller (via 813).

•

^{If the}

be a

MSR POST

contents were non-zero, it is assumed to

En!.!::! ... SYNCHENT

stack f r ame pointer. It wait bit in of that stack f rame i s turned otf, returns to the caller: (v ia R 13) .

R2 contains length of automatic storage

r - - - T

,

I B E l 00 Le ngth

'--_ _ _ _ _ --1. _ _ _ _ _ _ ___ -1. __________________ J

o 6 16 31

the and

The ENT routine computes t he total amount of stack sto.cagereguired by the user for linkage, save drea and his automatic data:

• If the reguirement cau be met from the current extension, the ne w re maining l ength is cal culated an d star ed.

• Else a st ack fcame pointer is set ~n 815 for the user, and chained ~nto t he stack.

• If bit 3 is OD in the MSR, SYNCHENT was entered due to an interrupt; the status infor ma tion is moved into the stack and ENT exits directly to the new routine.

• El se the PC in the interrupted stack frarue is set to the former contents of R14, R2 through R14 are loaded from the interrupted stack frame, and ENT exits directly to the new routine.

r---T----T----'

I L- _______ OB ~ I ___ 0 _ l I _ _ _ _ 0 J I

o ^{8 12 15}

The RET extended instruction handler sets R15 equal to the address of the previcus savea·rea:

• If there ~s no previous savearea, the stack

frame header is removed from the active queue and freed, and RET exits to the dispatcher.

Else i t computes the new remaining length:

• If the address of the next savearea in the

~avearea poillted to by R15 i s the same as the [ol:mer contents of !l15, RET stores the new I:emainillg length.

• Else i t is popping up from a stack extension, and frees the e xtension.

•

^{If the new} I:emaining length is equal to the total l ength, the header is dequeued, stack fralile freed, and Rr:T exi ts to dispatcher.

the the

nET t hen checks the status of the routine to which contl:ol i s about to be returned:

• If it is in a wait state, RET exits to the dispatcher •

• Else it returns directly to the new stack .frame.

2.3.2 DATil MANAGEMENT

The free memory is maintained in a linked list, with the pointer to the starter ele ~en·t i n the 11El'A 4A unit control Block. If the low order bit of this semaphore is one, t he META 4£ is using the gueue , and the META 4A must loop, waiting for the list to be f ree.

The entries are stored by ascending address, to facilitate concate nation of adjacent f ree areas. Each entry is of the format:

r--- T---' o

I next pointeT ,

t---t---~

2 Ilength of entry I

L _ _ _ _ _ _ _ _ L _______ J

next pointer: pointer to the next element on the free gu eue.

length of entry: the length of t his entry in bytes , i ncluding the header.

l;nlfY';' GET fl EM

&6 contains amount of storagE requiTed (in bytes)

65 --) new allocated area R6 contains rounded length

• normal -- t o caller via 014

• abnormal -- to PGftCHK

r---~----T----'

01 Ila I R 1 I

L- _ _ _ _ _ _ _ ..L _ _ ._..1. _ _ _ _ J

o 8 12 1 '5

r---,----T----,----r---, I L ________ 41 ~ I ____ Ra ~ I ____ X 1 ~ I ___ B 1 , ..1. ____________ 1;1 J I

o ^{B 1.2 16 2 0 31}

The GETMEM routine searches the free memory queue for the £irst entry long enough to sati sfy the request :

• If no entry long enough is found , GETMEN exits to PGMCHK to signal a No Free Memory program check.

•

^{If the entry matched the requested}

exactly, i t is dequeued and returned to the caller.

le ng tlt

its address

• If the entry is longer than the request, its length is decremented by the requested length,

and the address of the entry plus the length remaining is returned.

r---r----~---,

I 02 I Ra I Rl ,

L ________ ..1. ___ - L ____ J

o ^{B 12 15}

'fhe GETtiAX routine searches the free memory queue ior the largest element:

• If the gueue is null, GETMAX exits to PGi1CHK to signal a No Free Memory progr:am check.

~ Else it degueues the entry found and re turns i ts address to the user, exiting via R13.

ll.!!ln:.

FREEMEM

R6 --) area to free

R7 contains length of area to free

• normal -- to cal ler via R 14

• abnormal -- t o PGMCHK

r---T----T ----'

I 03 I Ra I Ell I

L _______ - L -___ ~ ____ J

o 6 12 1 5

r--- ---T----T

~--~------,

I 43 I Ra Xl I Bl I Dl I

L _______ --1.. _ __ __ .L _ _ _ .L-_ _ _ i. _ _ _ _ _ _ _ _ _ _ J

o ^{8 12 16 20}

FREEMEM searches the free memory que ue for dn entry with a forward pointer greater than the address to be freed:

• If unsuccessful, i t selects the last element on the list.

• It then c hecks to see if the end address of the sel ected elemen.: i s adjacent to the area to be

Ereed.

• If so, the length of that element is incr:emented by the le ngth to be freed .

• Else, the new el~ment is enque ued at that point. PREEMEM tnen examines the next element on the gue ue:

• If it is adjacent to the new el ement, i t is

degueued and the ne w element' H length adjusted accordingly.

2.3.3 INTEHPROCESSOR COMMUNICA1IONS

ll.!!.t£Y.i. S H OU L DE R

r---T---T---·-r----r---,

I 6 3 I 00 I X t I Bt I D t I

L _ _ _ _ _ _ _ ~ __ ~ _ _ ~_~ ____________ J

o 8 12 It) 20 31

The INT B extended start I/O to the IPI to has been acknowledged by

i Ilstruction handler issues a de termine if the last interr: upt the META 4B:

• If the last interr:upt is stil l pending, the

routine loops until the !ETA 4B acknowledges the interrupt.

• Otherwise, i t stores the interrupt code in t he META 41\ UCB Hni t ~ta t us Half word, a nd issues a start I/O to interrupt the META 4B.

2.4.1 STACK FRAME HEADER

r---~---,

o

Iparallel queue I

J---+---~

2 Ipriorityl!!!!!!!1

\ - - - + - - - - j 4 Istack frame sizel

~---+ ---~

16 SJ'P save I

L _ _ _ _ _ ^~ _ _ _ _ _ "

parallel 'lueue: this pointe r: is used oy .LEVELO to maintain a queue of the stack frames of eacl, of the paral le l

routines currently running on the system. The head of this queue is in memory location X'60 '.

priority: This byte contains the priority assigned to this parallel e vent. The priority is used by LE'ELO to decide which parallel e ve nt should he given control each time such a decision must be made.

stack frame size: This halfword contains the stack f rame size estimation made by the progr:ammer:.

SFP save : Whene ver the paralle l routine is not executing, i ts current SFP is saved ill this halfword.

2.4.2 STACK FRAME

SFP 1

r ---,

V

o

1previous pointer1

\---l 2 1 next pointer 1

/--- - -1

4 1 1

s av E area

1 1

\---·- - - 1

221 I

automatic storage

previous pointe r: this half word contains the address of the stack frame section of thE routine executing dynamically prior to this routine.

ne xt pointer: this pointer i s used byLEVELO to mai ntain

sa ve

the dynamic link of stack frame SEctions and is of no direct use to th programmer.

area: these 15 halfwords aJ:e used to store the routine's !IS R t hrou gh register 14 at any t ime his execution is dElayed due to an actual lUach in e interrupt or to a subroutine call.

automatic storage: This space is the actual automatic storage requested by the routine. It can VDJ:Y in size from 1 t~ n half words; this s ize is aetermine~ by the exte nded instruction ENT, which must be the

f!.£§.l

instruction of every routine that either saves the registers of the previous routine or requires automatic storage or both.

~ I I I

I

"

2.4.3 CPU UNIT CONTROL BLOCKS

U ni t control Bloc ks The CPU

in terprocessor I/O unit nCB's.

communications and vary

r---,---,

o

I 7 I

1---~---j

2 IInterrupt Code I

r---+---~

4 I --) MULTICOM4 I

~---+-----j

6 1 Freelist Flag⁵ 1

r---+---~

8 1--) I'reelist Head 1

L. _ _ _ _ _ _ _ --L ______ - '

are used for in format from the

4Initialized by MULTIPIC at execution t ime. SLow order bit used as F~eelist semaphore.

The 110 Supervisor handles all local IIC interrupts, and processes the EXCP extended instruction. Since the supervisor simUlates a virtual channel, the HCP and interrupt )J1:ocessing

are intimately related.

Some of the general purpose registers i,ave fixed contents during operation of the 110 Supervisor:

R3 --) cu·rrent CPC

R 10 --) Unit Control Block

H1S --) user's current save area

]nl£Y.i r~ X C PDr S P

R10 --) HCB

R5 contains current operation The possible operations are:

•

^{0 EXCP}

•

^{1 R Ell D}

•

^{2 WRITE}

•

^{3 NOP}

•

^{4 SENSE}

•

^{5 SEN SE} with reset

•

^{6 SPECIAL}

• 7 - - In ter:r: upt

The dispatcher: uses the code in 85 as an index into t he IhAr:e to Go table in the UCB. I t then uses the byte at tllat offset in the UCB ITG table to index into the global ITG table. Since

III any of the entries, e. g. NOP, SENSE, SENSE with reset, arA identical, this saves s pace fr:om i ndividual WTG tables.

3.2.1 EXCP ROUTINES

The insur:ing opera tion.

EXC P that

routines the unit

are ge ner:ally r:esponsible for i s read y before starting an I/O

R3 ^{- - )} cu r:ren t CPC R 10 ^{- - )} UCB

RD ^{- - )} re tur:n point

R 15 ^{- -)} user's c ur:re nt save a rea.

J;;!LtIY~ COM SIO

unit:

The cornman s tart I/O routine issues a sense to the

• If the USH re turned indicates that the unit i s bus y or offli ne, COMSIO sets the condition 60de appropr iate ly in the user:'s stack fr:ame and exits via R13.

• Else COBSIO continues into CeMRDY.

]nlIY';' COl1RDY

EXCP

COMROY is entered Dispatcher:, if

from COMSIO or dir:ectly from the the device cannot be offline. I t

set.s the "logically busy flay on in the ueB and calls CPC processing⁶ via R9.

3.2.2 INTERRUPT ROUTINES

R 3 --) cur:rent CPC R10 --) [JCB

R15

-->

interrupted task's current save area

The interrupt routines are completely unit dependent.

l'hey do share some cemmon character:istics:

• They check for error:s, and either retry the

operation or set the device Don-busy and exi t to SIGNALEV to signal an error event.

• Else they check for operation complete:

• If the operation on the CPC is complete, they call CPC processing via 89 at entry COMINTEN to continue processing on the CPC chain. When control is r:estored, they exit to SIGNALEV to signal the operation complete event.

• Else, they issue the next start I/O in the sequence and exit to the interrupted task.

3.2.3 META 4B INTERRUPT PROCESSING

When the I/O Supervisor recognizes an interrupt from the META 4B, it retrieves the interrupt code from the USH in the tlETlI 4B UCB, acknowledges the intErrupt, and e xits to SIGNlILEV to signal event X'1031', with the interrupt code as its status.

6Yig~ Section 3.4

,

J

,i

]ni£Y.i EXCP

, r---,.--- ---r----,--- ---T----T --- - -,

I PO I 00 I Bu I Du I Be I De I

L _ _ _ _ _ _ ^~ _ _ _ __ _ _ ^i__~ .i ____________ J

o 6 16 20 32 36 ⁰⁷

The BXCP routine sets 810 to pointer to the proper DCB, sets R3 to point at the use r' s CPC, then tests the UCB flags:

• If the unit is logically busy, i t sets the condition code appropriately in the user's stack frame and exits via R 13.

• El se i t enters the EXCP dispatcher with a 0 in 85.

llni£Yl C 0i'1I N'r ED

Il3 ^{- - )} current CPC

R9 ^{- - )} retur n point Rl0 ^{- - )} UCB

ll15 ^{- - )} UEer's current sa ve area COMINTRO is

t he current CPC CPC, clears out t.hem in R14:

the common CPC interpreting loop. It stores address in the UeB, picks t.hE opcode from the

the high crde r four bits, and places a copy of

• If the opcode is greater than 7, it exi ts to SIGNALEV to signal an I.nvalid CPC program check (X '0024 ').

• I i the opcode is egual to 7 (TIC) , i t picks up the ne"

epc address and goes back to the start of the loop.

• Else i t calls EXCPDIS P via R4, with t.he CPC opcode in R5 t.o call the unit dependent routine.

When i t ret.nrns, it. checks the immediate operation flag in the flCB:

I II

---.

• If i t i s off, an interrupt is expected, and COMINTRD

~etu~ns to the caller via R9.

• If it is on .. cor1INTRD checl{s for chaining in the epc fla gs:

• If chaining i s indicated, COMINTHD tumps R3 by 6 and

~e-enters the leap.

• Else it resets the "logically busy" f lag in tlte UCB ano exits via R9.

3.4.1 UlH'r DEPENDEN'L ROUTINES

R3 --) current (PC H4 --) return point

R9 RESERVED

11 10 --

>

UCB

R14 contains mooifier fiel d of CPC R 15 --) useL" s current save area The uni t

operation, set is in prog ress

dependent routines generally start an I/O a flag in the UCB to indicate what operation a no the n e xi t via R4:

• If the operation completes immediately, the

immediate operation flag is set in the DCB flags.

llni£Yl

ZLIOH

ZLIOH sets R10 and R3 to point to the interrupting unit's DCll and cur~ent CPC respectively. I t then checks the I/O old

NSR:

..

^{If the iutel:rupted task lias in}

the expected CPU interval contents of the timer •

a wait state, i t sets egual to the current

. I t t hen checks the inte'~rupting unit's address:

• If the interrupt was from the META 48, i t goes to the META 48 interrupt handler⁷

• Else i t branches to EXCPD~SP with d 7 in R5, indicating an interrupt.

The Timer contrel cede allows the LEVELl us~r to keep track of running and CPU time, and to set time intervals.

3.6.1 T~MER INTERRUPT ROUTINE

~!li£Y.:. GRANDDAD

The Timer Interrupt Routine calls UPTIMER to update the CPU and Running til1'es. I t then sets a new time interval in the Timer, and checks to see if a time interval set by the user has expired:

• If the user's interval has not expired, it returns directly to the interrupted routine •

• Else i t exits t.o SIGNALEV to s ignal event X'200 1 '.

3.6.2 Q'l'IMER INSTR ucnON

1ll!1I.E QTI MER

r---T---T----.---r---- - - ,

I 64 I ()

a

^I xt I 8 t I Dt I

L _ _ _ _ _ _ - L ____ ~ ____ ~ _ _ _ ~ ____________ J

o ^{6 12 l~ 20 31}

The QTIMER routine calls UPTIMER to get. the up to dat.e time, then moves the RUNNING ani! CPU times from the DC!3

7~~1~ Section 3.2. 3fo1: de tails.

extension to the user's aeea, and exits dieectly to the user ..

3.6. 3 UPTIMER ROUTINE

12nll:.Y.i U PT I lIE R

lKli§.i

to call ee via R13

UPTIMER is called by the dispatcher wchen it is about to go i nto a wait state ; i t i s called by the Timer:

I ntereupt Routine to update the clocks; and it is called by QTIMER to get the corrected times.

It s ubteacts the contents of the Timer from the e xpected inteeval, then adds the computed value to the 32 bi t clocks. It then replaces the expected inteeval with the contents of the Timer. This code , combined with the setting of the CPU expected interval by the I/O intereupt handler should maintain the CPU a nd Running ti me 32 bit clocks.

3.7.1 UNIT CONTROL BLOCK

The unit ContLol Block contains the device independent information for each device and illost of the residual control info.rmation needed to simula te the virtual channel :

r---~---,

o

^{I unit addLess 1}

~---+

1

2 1 unit status I

l---+---~

lj IreseLved lfor Gf1S1 I---+---~

6 1 flag bytes I

l---+---~

8 1--) current cpe 1

\---+---~

101 sense race 1

t---+---~

121 ^II w/reset ^II 1

\---+---1

141 offlinel f l a g s j

t---+---~

161 j 1

where to go table

1 1

\---+---1

24 1 u nit dependent I extension

• •

unit address: vi'Ltual unit addLess.

unit status: USH from last SIO or inteLrupt.

reserved for ^GMS: unused in all ueB's except fer disk.

wheLe i t is used for Dr. Memory communications.

f lag bytes: residual control bits:

byte 0:

bit 0: logically busy; set at start of EXCP; reset at operation complete

I

bit 1: immediat.e; set if CPC operation was i mmedia teo

bit 2: verify (dis k only) .; c ylindec address must be veri f ied before write .

bi t 3: mul tisector (disk only) ; mu lti sec tor:

operation in progr:ess.

bits 4-7: unused.

byte 1:

bi t 0: write.; l~rite operation in progress.

bi t 1: r ead; read ope ration in pr:ogress.

bi t 2: verifying (disk only) ; cylinder address is being ve.rified.

bit 3: contr:ol; contr:ol operation in progress. bits 4- 7: unused.

The BUGSUCB macro is used to gener:a te the Unit Control Blocks and to generate a DSEC'r of the UCB's:

label BUGSUCB addr,offline,sense, senser, (wtg- list) [ ,ONITX=si ze]

l abel: name of UCB.

addr : virtual unit. address

offline: sel f def ining term for bits which if set indi cate that the de vice is bus y or offl i ne.

sense: hex code for 2nd half of sense

Iecc.

senser: he x code for 2nd half of sense w/reset 10CC. wtg-l ist:names of pointers in global Where to Go Table

for: device depende nt r:cutines .•

size: number: of halfwor:ds for unit depende nt extensions to UCB.

If TYPE=DSECT is speci fied, a DSECT rather than a r:eal UCB will be assembled.

The nCB device deFendent extensti on lnterval Timer co I;tains the running clocks information neccessary to control them.

r----~---,

24]time precision ]

~---+---~

26]time interval ]

~---~---~

28 1 RESERVED 1

~---+---~

30 1 CPU interval 1

~ -t--- ---l 321 running ,I

~---+----~

1 time 1

~---t---l

36 1 CPU I

r---+---~

1 time 1

~----+ -l 401 expiration ]

~---+---~

I time I

L _ _ _ _ _ _ -'- _ _ _ ~

for the and the

timer pr:ecision: 'time inte,rlfal to be set 'Ihen 'l'ime'r:- expires.

t ime inter:val: amount of time expected to have passed when a Timer interrupt occurs.

CPU intervdl: amount of CPU time expected to have passed wIlen a Timer interruFt occ urs.

running t i me: t ime in timer units since IPL.

CPU time: CPU time in timer units since IPL.

expirat.ion time: time at which LEVELl ',/ishes t o receive an interrupt.