SUPPLEMENT PDP

F-15(lO-4S)

P D P

SUPPLEMENT

( PDP-1D-45 )

DIGITAL EQUIPMENT CORPORATION • MAYNARD, MASSACHUSETTS

PDP-1D-45 SUPPLEMENT

F-15(lO-45)

Copyright 1964 by Dig ita I Equ ipment Corporation

ii

FOREWORD

This supplement describes special instructions added to PDP-l D-45 at Bolt Beranek and Newman. They are grouped as follows:

Memory Reference Instruct ions Load Character (LCH) Deposit Character (DCH) Twos Complement Add (TAD) The Skip Group

The Spec ia I Operate Group The Input-Output Transfer Group

CONTENTS

Memory Reference Instruc tions . . . . LCH . . . .

LCH Octal Code 13 .••...•.•... 2

DCH Octal Code 14 ..•...•.•... 4

DCH Octal Code 15 •. . . • . . . 5

TAD Octal Code 36 ... 6

The Skip Group. . . 7

The Special Operate Group... . . . 7

In/Out Transfer Group Instruction List . . . 11

Memory and Processor Control lOPs ... 11

Miscellaneous Processor lOT's.. . . 11

Type 23 Drum 10TI s ... 12

Data Communication System Type 630 . . . 12

Display lOT's... . . . 12

In/Out Transfer Group Detailed Description ... 12

Prec ision CRT Display 30 • . . . 12

Character Gen erator 33 ... . . . 1 3 Parallel Drum 23 ...•...•... 15

Data Communication System . . . 17

v

4K 4K 4K 4K MEMORY CONTROL

121C DRUM

SYSTEM TYPE 23

PO

I 0

r - - PROCESSOR PI

-

DATA COMMUNICATION

SYSTEM TYPE 630

PDP-ID-45

P2 I

I I I

I I~TUR-;I I I

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PROCESSOR

I-- -

~ L_P3_~

4K

MEMORY CONTROL

121C

I I I

I

4K

MEMORY CONTROL

121C

r - T - l

~-+-1

L_..L_~

r FUTURE "I

I MEMORY I

L -T-....J

^{EXPANSION I}

- -

^{- - - - .... 0}

I I

I

I - - ---1

I ¹

I

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PRIORITIES

- -

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PDP -10- 45 SYSTEM

Programmed Data Processor PDP-l D-45 System

MEMORY REFERENCE INSTRUCTIONS

LCH - Octal Code 12 - Load accumu lator with a character from memory.

DCH - Octal Code 14 - Deposit a character from accumulator in memory.

Each of these instructions is interpreted as being deferred, hence requiring three memory cycles for execution. The MB and AC are divided into three sections of six b its each. Bits 0-5 = character one

(l),

bits 6-11 = character two (2), and bits 12-17 = character three (3).

2

11 112

3

17

The instructions are sub-decoded from MB bits 0 and 1 during the defer cycle. MB bits 0 and are placed in the load-deposit register (LD) and decoded:

Octal Code 12 and LD - 01

=

LCl - Load character one loads accumulator from memory bits 0-5 and places in accumulator bits 0-5. (AC

O _

5)

Octal Code 12 and LD - 10= LC2 - Load character two loads accumulator from memory bits 6-11, and shifts into AC bits 0-5.

Octal Code 12 and LD - 11 = LC3 - Load character three loads accumulator from memory bits 12-17, and shifts into AC bits 0-5.

Octal Code 14 and LD - 01 = DCl - Deposit character one deposits accumulator bits 0-5 in memory bits 0-5.

Octal Code 14 and LD - 10 = DC2 - Deposit character two deposits accumulator bits 0-5 in memory bits 6-11.

Octal Code 14 and LD - 11

=

DC3 - Deposit character three deposits accumulator bits 0-5 in memory bits 12-17.

LCH

The registers below show a single step sequence through the LCH instruction if 100

8 is the starting location, and it contains a 128 to address 1000

8, The LCH instruction automatically forces a defer cycle. During the defer cycle, the memory address (MA) contains 1000

8, and the contents of the MB contain a 01 in the XX position and 2000

8 in the address portion of the

MB. During cycle one, 2000

8 would be the address. If the MB at this time is assumed to contain A, B, and C, the character A is transferred into the accumulator and the remaining 12 bits are cleared as shown in Figure a. During the defer cycle, if the XX portion of the MB contains 10, the character is transferred into the accumulator and the last 12 bits are cleared as shown in Figure b. If the XX portion of the MB contains 11 during the defer cycle, the results would appear as shown in Figure c.

CYCLE ZERO MA

[000' 001 '000'0001

DEFER CYCLE

CYCLE ONE

1010' 000' 000' 000

I

Figure a

Figure b

Figure c

MB

1001' 010'001 '000'000'0001

Ixxo'

000'010' 000' 000 ' 000

I

A B C

A ACCUMULATOR 1110'001' 000' 000'000' 0001

B

11 1

a

^I

a

¹

a '

^{000 I 000 I 000 I 000 1}

C

III a

^I

a

^{11 I 000 I 000' 000 I 000}

I

The LCH instruction clears AC bits 6-17 and leaves the single character in AC bits 0-5.

Ixxx

^{XXX 000 000 000 000 r}

LCH Octal Code 13

When the defer bit is a 1 during cyc Ie zero, it sets a one to the increment fl ip-flop (INC) placing the instruction in the automatic increment mode. In the defer cycle, this takes the first two bits of the MB and effectively adds one

(+

1) to them. The first time this is used or to enter the automati·c mode, the first two bits of the MB should be zeros as the incrementing takes place before the character handling cycle (cycle one).

When entering the defer cycle if the address contains a:

loox ^{XXX X}

It is incremented to contain:

101

If entered with a

01,

it is incremented to:

A lOis incremented to a:

In the last situation, an 11 causes the character bits to be forced to a 01 and the address portion of the MB to be incremented by one.

-401

l __ ' ________________________________ )1

plus one Summary: In the automatic mode a sequence performs as follows:

00 -

Loads character one 01 - Loads character two 1 0 - Loads character three

11 - Increments the address (+1) and loads character one in the new address

01 -

Character two

10 - Character three

11 - Plus one to address and loads character one in new address

01 -

Character two

10 - Character three

11 - PI us one to address and loads character one in new address

3

NOTE: If the automatic mode is entered with a 01 in the first two bits of the memory location brought out during the defer cycle, the first character is skipped.

If a 00 is used in the non-automatic instruction, it is interpreted as a LC 1 (01) and loads the accumu lator from memory bits 0-5.

In the automatic mode a mid-instruction break is not allowed be- tween the defer cycle and cycle one. (No sequence breaks can occur between the defer cycle and cycle one).

DCH Octal Code 14

Assuming a sequence of cycles as used in the LCH instruction, if the accumulator contains a series of characters thus:

/A ^B ci

and the memory location addressed during the defer cycle contains a DC1 (01) in the first two bits, at the end of cycle one the AC would contain:

IB c

The MB:

xxx

^XXX XXX

xxxi

The XiS indicate the information originally contained here remains unchanged.

If the memory location addressed during the defer cycle contains a DC2 (10), and the AC initially contains

A B

C

The result in the AC would be

B c

^A

In the MB

Ixxx

^{XXX A}

Ixxx xxxi

A DC3 (11) provides the following results in the AC and MB if the AC initially contains the ABC.

AC B C

A

MB

Ixxx

^{XXX XXX XXX} A

The following is the result left in the AC and MB if a sequence of DCH instructions is used (non-automatic) and the AC initially contains an ABC in that order:

DCl

AC B

C

A

MB

A x x

DC2

AC

C A

B

MB

A

B

x

DC3

AC A

B

C

MB A

B C

Summary: The DCH instruction always takes the character that is in the first six bits of the AC and places it in the character position designated by the first two bits decoded in the defer cycle: first character to first position, first character to second position, or first character to third position.

DCH Octal Code 15

The DCH instruction, using the indirect address bit (bit 5) of the word as a 1, sets the INC fl ip-flop and during the defer cyc Ie increments the sub-instruction through the same sequence as shown for LCH. The automatic mode should be entered with a 00 in the location addressed

in the defer cycle. (Reference from AC to MB)

DCH 00 - Deposits first character in first position.

DCH 01 - Deposits first character in second position.

DCH 10 - Deposits first character in third position.

DCH 11 - Increments the address and depos its the first character in the first position of the new address.

5

If the alphabet were typed in by a program sequence it might resemble this:

Start cia Vclf szf i (1)

i

^mp.-1 tyi rcr (6) sad (77)

hit

dch i store imp start

/ clear accumu lator and flag 1 /1 isten loop

/bring in typed character / move from I/O to AC

/ compare for end character (77)

The MB storage locations would be packed thus:

1 2

3

4

5 6 7

10

11

A D G

J

M

P

S V

Y

B C

E F

H I

K L

N

0

Q

R

T U

W X

Z

Summary: The DCH instruction deposits the accumulator bits 0-5 into the character location of the memory buffer spec ifi ed by the bits 0, 1 of the location addressed in the defer cycle, and rotates the next character or that character contained in accumulator bits 6-11 into accumulator bits 0-5 so that it might be deposited in memory on the next use of this same DCH instruction.

If the automatic mode is entered with other than a 00, a character is skipped.

A 00 used in the non-automatic mode is interpreted as a 01 . TAD Octa I Code 36

TAD - 2¹s complement add

The state of the link is sensed, and if a ONE, one is added to the AC

(+1

to AC).

The C(Y) are then added to the C(AC). The result is left in the AC and the original C(AC) are lost. The C(Y) are unchanged. A carry out of bit

a

is retained in the link fI ip-flop.

THE SKIP GROUP

644000

SNI Skip on non-zero I/O

Tests the I/O register for the presence of a one. Skips the next instruction in sequence if any of the I/O bits is a one.

654000

SZI Skip on zero I/O

Tests the I/O regis.:!r for the all-zero condition.

Skips the nex' Instruction in sequence if it exists.

760020

LIA Load 1/0 register feom AC

Loa,";sthel/O register from the accumulator

760040

LAI Load accumu lator from I/O

Loads the acc umu lator from the I/O reg i ster

760060

SWP Exchange AC and I/O

Places the origina I contents of the AC into the I/O and the original contents of the I/O into the AC

770000

CMI Complement the I/O

Is the logical NOT of the contents of the I/O register

THE SPECIAL OPERATE GROUP

The spec ial operate group of instructions is a new set of microprogram instructions. It uses octal code

(74).

Execution time is 5 microseconds.

The ring mode is also handled by the special operate group. The ring mode flip-flop (RNG) is set, cleared, or sampled with the program flag instructions. Its condition is transferred to I/O bit

11,

and it can be set by the condition of I/O bit

11 .

Ring mode is the condition whereby the address portion of the word can be caused to loop re- petitively over a section of memory. Ring mode is an eight location loop, starting with the three least significant bits in the address portion of the word. It is indexed to seven

(111

2) and then back to zero

(000 2 ).

See figure at end of SPC group on page

11 .

7

Three instructions are affected by the ring mode: the load or deposit a character (LCH + DCH);

index a character (I DC); and index the accumulator (IDA). Ring mode does not affect the add or normal index instructions (ADD or IDX). Setting, clearing, or sampling of the RNG flip- flop can be thought of as program flag zero.

The I ink fl ip-flop has been added to the accumulator to receive the carry out of AC O ^{in 2}

1s complement add (TAD). The I ink fl ip-flop is placed in I/O bit 10 when transferring the con- tents of the program flags to the I/O. It is set when transferr ing the contents of the I/O to the program flags by the condition of I/O bit 10.

5 Reverse

Skip

744000

6 IIF

Event Time

1

Event Time

2

Event Time

3

Event Time

4

7 8

IFI IDC

IIF

Event Times

SCI SCF Cll SZl

SCM IFI /IF

IDA CML

IDC

Bit Configuration

9 10 1 1 12 13 14 15

16

IDA SCM SCI SCF SZl Cll CMl X

Inclusive OR of the I/O from flags. Forms the inclusive OR of the I ink, RNG, and program flags 1 through 6 in I/O register bits 10 through

17

link -

1/010

Ring Mode -

1/011

Program Flag

1 - 1/012

Program Flag

2 - 1/013

Program Flag

3 - 1/014

Program Flag

4 - 1/015

Program Flag 5 -

1/016

Program Flag 6 -

1/017

If used with SCI, the I/O is cleared prior to readin.

17

X

742000

IFI

741000

^IDC

Inclusive OR of the flags from I/O. Forms the inclusive OR of I/O register bits

10-17

and leaves in the link, RNG, and program flags

1

through 6 respectively.

1/°

10 =

Link

1/011

= Ring Mode

1/012

= Program Flag

1 1/013

= Program Flag

2 1/014

= Program Flag

3 1/015

= Program Flag

4 1/016

= Program Flag

5 1/017

= Program Flag

6

Index character

Indexes bits 0 and 1 of the AC. Operates as a pointer word for the LCH or DCH instructions

/ +

1

AC

O _

1 -I

^to

11 - )

to AC

1

_ /+1

AC

O _

1 -

to

11 - )

to AC

O .

The end around carry then causes the address portion of the word to be indexed.

See figure below.

Start

00

01

10

11

01

Repeat

9

740400 IDA

740200 SCM

740100 SCI

740040 SCF

740020 SZF

740010 Cll

740004 CMl

Index Accumu lator, Adds one to the contents of the AC (no effect on MB).

Special Complement

Complements the accumulator and adds one to the accumu- lator if the I ink b it was a one. (Does not perform the 2¹s complement in itself.) ANDed with IDA the 2¹s complement - complement of a number is obtained.

Special Clear

I/O

Clears the

I/O

register at the first event time.

Spec ial Clear Flags

Clears the link,

RNG

and the six program flags.

Sk ip on zero I ink

Sk ips the next instruction in sequence if the I ink is a zero.

750020 wi" skip the next instruction in sequence if the I ink is a one.

Clear link

Clears the link flip-flop at event time one.

Complement link

Forms the logical negation of the I ink. If a one it is changed to a zero. If a zero it is c hanged to a one.

RNG

Address portion of MB

Ixxx XXX XXX 000 I

001 010

all

100 101 110 '111

I ^{XXX XXX XXX 0001}

IN/OUT TRANSFER GROUP Memory and Processor Control lOPs

720011

ERG Enter Ring Mode

720010

LRG Leave Ring Mode

720064

LRM Leave restrict mode

720065

ERM Enter restrict mode

720066

RNM Rename memory

720067

RSM Reset memory banks

Miscellaneous Processor IOTl s

72XX32

RCK Read clock

72XX35

CTB C I ear trap buffer

72XX17

RRO Rem -rand out

72XX37

RRI Rem-rand in

11

72XX61 * 72XX62*

720063*

722061 722062

720022 721022 725022 724022 720122 724122 721122

720007 722027 720027 720127 722026 720026 722007

720007

DIA DWC DCl DBA DRA

RCH RCR TCC TCB RRC SSB RSC

DPY GPl GPR GCF GlF GSP SDB

DPY

Type 23 Drum 10TI s Drum initial address Drum word count Drum core location Drum break address Drum request address

Data Communication System Type 630 Rece ive a character

Receive a character and release the scanner Transmit a character from receiver counter Transmit a character from send buffer Read the receiver counter

Set the send buffer

Clear flag and release scanner Display 10TI s

Display one point (intensify) Generator plot left

Generator plot right Reset

load format Space

load buffer, no intensify Prec is ion CRT Display (30)

Display one point. Clears the light pen status bit and displays one point using bits 0 through 9 of the AC to represent the (signed) X coordinate of the point and bits

o

through 9 of the I/O as the (signed) Y coordinate

AC bits 0-9 and I/O bits 0-9 are loaded before the DPY instruction is given. The line specified by the AC is the signed X coordinate. Plus

(O)

in AC bit 0 plots points from the center of the

*Above must be given in sequence shown.

cathode ray tube to the right 4-5/8 inches. Minus (1) in AC bit

a

plots the points from the center of the tube to the left 4-5/8 inches. The line specified by the I/O is the signed Y coordinate. Plus (0) in I/O bit

a

plots points vertically up from the center. Minus (1) in I/O b it

a

plots the po i nts from the center down.

722027

720027

720127

x = 1000 • y = 0777

x = 1000 • y = 0000

x

=

1000 y = 1000 •

GPL

GPR

GCF

x =

•

0000 y = 0777

x =

•

0000 y = 0000

x = 0000 y = 1000

•

Character Generator (33)

• x = 0777 y = 0777

• x = 0777 y = 0000

x = 0777

• y

=

1000

Generator plot left. Transfers the contents of the I/O register of the symbo I.generator and in itiates plotting of the first 17 dots.

1/0

17 of this word sets or resets the subscript control as the bit is a

1

or a

O.

Generator plot right. Transfers the contents of the I/O register to the shift register of the symbol generator and initiates plotting of the last 18 dots. The "C lear" is inhibited by

MB~

to prevent losing the count contained in the horizontal and vertical counter which controls dot position.

Reset. C I ears the light pen status fl i p-flop in the d ispl ay . The light pen status wi II a Iso be c I eared when a norma I point plot (lOT -07) is performed.

13

722026 GFL Load format. The three least significant bits of the I/O register are sent to the character-size control flip-flops and the spacing control circuits. Bits 16 and 17 specify one of four symbol sizes as shown in the tables below.

Bit 15, if a 1, specifies automatic spacing between symbols.

A completion pulse is not generated by the display when this instruction is performed.

Matrix size, and hence character size, is determ ined by the number of increments separating the dots on the matrix, when an increment is defined as 1/1024th of the width of height of the display area. The relationship between character size and incremental separation of dots is given below.

Character Size

1 2

3

4

720026 GSP

720007 DPY

722007 SDB

Bit 16 Bit 17 Number of

Increments

0 0 2

0 1

3

1 0 4

1 1 5

Space. Increments the X buffer-counter to position the beam one character position to the right. Since the contents of the I/O register are transferred to the shift register by this instruction, the I/O register should be cleared before performing the ^II Space ll instruction.

Load buffer - intens ify

Load buffer - no intensify. By use of the MB12 bit, the normal point plotting instruction (lOT -07) can be used to load the pas ition coordinates of the first character to be displayed without illuminating that point. When the ^II No

Intens ifyll instruction is performed, the display wi II not generate a completion pulse; therefore, the computer must allow at least 25 microseconds before executing a gpl instruction.

Except for the gcf, glf, and sdb instructions, which do not cause the generation of a completion pulse, the preceding iot instructions can be coded to perform the in-out wait operations.

72X061 *

DIA

720062*

DWC

720063*

DCl

722061

DBA

720064

lRM

Parallel Drum

(23)

Drum initial address

Transfers the contents of the I/O register to the drum and is decoded to mean:

100

1 = Read

101-5

= Field to be read 1°6_

7 ⁼ Drum initial address Drum word count

Transfers the contents of the I/O reg ister to the drum and is decoded to mean:

10~

^{= Write}

101_5

= Field to be written 1°

6 -

17

⁼ Words to be transferred Drum core location

o ⁰

102 - 103

= Select memory

0

o

1

102 - 103

= Select memory

1

1 0

102 - 103

⁼ Select memory

2

1 1

102 - 103

= Select memory

3

1°4_

17

⁼ Starting core address and GO ~ Drum break address

Is decoded the same as DIA. When a DBA instruction is given, a sequence break occurs when drum address = drum

initial address. If programming consideration can accept the break, DBA can be used in place of DIA in the drum sequence of instructions.

leave restrict mode

Zeros the restricted mode fl ip-flops. No memories are protected. All instructions are legal except incorrect OP code selections.

*

Above must be given in sequence shown.

15

720065 ERM

72XX66 RNM

720067 RSM

720032 RCK

72XX35 CTB

Enter restrict mode

When entering restrict mode, the i/O register should be preloaded with the desired memories to be protected.

100 1

=

Protect memory 0 101 1

=

Protect memory 1 1°1

2

=

Protect memory 2 103 1 = Protect memory 3

When in the restrict mode if an incorrect operation code, in-out transfer (lOT), a HL T or any protected memory is addressed, it causes the restrict mode logic to initiate a break to channel 16

8 in the sequence break logic.

Rename memory

Rename memory takes the memory des i gnat ed' by X and renames it to the number contained in Y. There are four memories and they can be named in any of 16 different configurations. All addressed memories are checked for name. Memory rename logic cannot be bypassed. See RSM.

Reset memory

Restores the physical name to all memories. Zero is a zero, etc.

Read clock

The I/O is cleared and the clock buffer is read into the I/O register.

The c lock register is automatically synchronized to the computer timing, and it is not necessary to read clock reg ister more than once. The clock is a pu Ise at a 1 kc rate and can be read as often as des ired.

C I ear trap buffer

The trap buffer (which is loaded at the time a restrict mode trap occurs) is cleared by this lOT.

72XX17 RRO

72XX37 RRI

720011 ERG

720010 LRG

Rem-rand out

Transfers the condition of the I/O register bits 0-17 to the Rem-Rand Control.

Rem-rand in

Clears the I/O and reads the conditions of the Rem-Rand Control into the I/O register bits 0-17.

Enter ri ng mode

Places the computer in the ring mode. (See spec ia I operate group for detailed description.)

Leave ring mode

Zeros the ring mode fl ip-flop.

Data Commun ication System

The 630 Data Communication System is assigned one basic lOT instruction, octa I code 720022.

(Bits 0-17)

The basic instruction is microprogrammed to form a set of useful computer instructions for oper- ating the DCS. Adding or ORing 2000

8 to the octal equivalent causes the I/O to be cleared before the operation is executed.

The fo 1I0wing instructions contro I the scanner, the teletype transm itters and teletype rece ivers.

For convenience, bit configurations are assigned mnemonics as follows:

720022 RCH Receive a character to I/O 10-17 (8 bits) {13-17, 5 bits}

721022 RCC

725022 TCC

using the receiver counter. The OR function occurs. Clear the receiver flag. I/O bits 10-17 must be zeros prior to operation execution.

Same as RCH. C I ear the scanner flag {rei ease the scanner}.

Transmit a character using the receiver counter (I/O 10-17, 8 bits; I/O 13-17, 5 bits, to the transm itter). C lear the receiver flag. Clear the scanner flag {release the scanner}.

17

724022 TCB

720122 RRC

724122 SSB

721122 RSC

T ransm it a character us i ng the send buffer (I/O 10-1 7, 8 bits; I/O 13-17, 5 bits, to the transmitter). Clear the receiver flag.

Read the receiver counter (counter to I/O 12-17). The OR function occurs.

Set the send buffer (I/O 12-17 to send buffer). Used to select an idle station for transmission.

C I ear the scanner flag (rei ease the scanner).

The state of the scanner flag may be read into I/O register bit 16, using the check status instruct ion (1 = fl ag on).

Initialization procedures must at least include clearing of the scanner flag. (Actually all receiver flags should be cleared.)

The priority level to which the scanner flag is assigned is dependent upon the equipment con- figuration of your system.

6056 ^P~INTED IN U.S.A. .5-6/64