A Secure Lightweight Hardware‑Assisted Charging Coordination Authentication Framework for Trusted Smart Grid Energy Storage Units

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ORIGINAL RESEARCH

A Secure Lightweight Hardware‑Assisted Charging Coordination Authentication Framework for Trusted Smart Grid Energy Storage Units

Fathi Amsaad¹ · Selçuk Köse²

Received: 31 May 2021 / Accepted: 25 August 2021 / Published online: 4 September 2021

Abstract

Smart plug-in electrical vehicles (PEVs) have recently become essential components of the energy storage units (ESUs) in a smart power grid network. ESUs need to frequently communicate with charging stations for authentication before their battery systems are securely and efficiently charged. In this paper, an efficient lightweight hardware-assisted authentication and key management framework for ESU based charging coordination system is proposed. The framework integrates a hybrid lightweight arbiter linear feedback shift register (ALFSR) physical unclonable function and a low-cost advanced encryption standard (AES) for more secure, trusted, and robust secret key scheme. The scheme is implemented and validated on a reprogrammable device using 28 nm Field Programmable Gate Arrays (FPGA) platform. The results demonstrate that our framework can generate inherently unique and reliable secret keys. The proposed scheme is efficient in terms of key storage requirements and satisfies the authentication time of five security levels required by National Institute of Standards and Technology (NIST). Furthermore, the resilience of the proposed ALFSR is analyzed against ML modeling attacks, including k-nearest neighbor (kNN), kernel support vector machines (KernelSVM), and artificial neural network (ANN) which aim to clone the PUF behavior and compromise the secret key. The preliminary results demonstrate that the ALFSR PUF design is less vulnerable to kNN and SVM ML attacks as compared to ANN attacks.

Keywords Energy storage units · Physical unclonable functions (PUFs) · Smart grid security

Introduction

Smart plug-in electrical vehicles (PVEs) are one of the popular smart grid energy storage unit (ESU) products developed by the automotive vehicle industry and act as a renewable energy source that enhances the performance, reliability, sustainability, and power delivery of smart grid systems [1–5]. Even though PVEs accompany various benefits to

enhance the flexibility and performance of the smart power grid, their wireless charging system introduces many security and privacy issues that need to be addressed [1, 12–15].

Most of the existing secure charging coordination systems house a protocol-based secure solution and do not sufficiently address the security issues related to robust real-time hardware-assisted authentication schemes, strong secret key generation and management, and the mitigation of possible cyber-physical system and modeling attacks against smart power grid charging coordination systems [16–21]. There is therefore an instant need for an effective and robust hardware-oriented security scheme to enable trust in the smart- grid charging coordination systems by preserving the privacy and security of the communication among the PEVs and the charging stations, and protect smart PEVs against emerging CPS security threats [1, 6–11].

Silicon physical unclonable functions (sPUFs) emerge in hardware-assisted security to achieve robust device authentication and secret cryptographic key generation. sPUFs provide a low-cost hardware-assisted security solution

This article is part of the topical collection “Technologies and Components for Smart Cities” guest edited by Himanshu Thapliyal, Saraju P. Mohanty, Srinivas Katkoori and Kailash Chandra Ray.

* Selçuk Köse

selcuk.kose@rochester.edu Fathi Amsaad

famsaad@emich.edu

1 Eastern Michigan University, Ypsilanti, MI, USA

2 University of Rochester, Rochester, NY, USA

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supporting authentication and encryption within a relatively easy and lightweight configuration, ideal for intelligent and energy-constrained IoT devices [22–24]. sPUFs take advantage of intrinsic manufacturing process variations during the IC fabrication to generate unique, reliable, and genuinely random binary secret keys utilizing the related challenge- response pairs (CRPs). The generated PUF-based secret keys can be used as device-specific identifiers (IDs), eliminating the need to store the private secret keys in nonvolatile memory (NV) and also overcoming the added design complexity, high computational time, and large overhead.

The security of sPUFs is becoming an increasing matter of concern due to their vulnerability to emerging machine learning (ML) and modeling attacks [25, 26]. An attacker can use ML attacks to emulate the behavior of an sPUF using a subset of the PUF’s CRP space which can be obtained legitimately. An attacker then can train ML algorithms using the PUF’s CRP information to predict or model the complete CRP space of a PUF design.

A hardware-oriented framework performing end-to-end authentication and encryption for a secure and trusted next- generation smart grid charging coordination system is proposed in this paper. The proposed framework is based on a lightweight arbiter linear feedback shift register (ALFSR) PUF, and low-cost AES encryption. Unique silicon signatures (authentication and encryption keys) can be generated using this framework.

A summary of the main contributions of this work to address the security/privacy issues in smart power grid charging coordination systems are as follows.

– An efficient hybrid lightweight hardware-oriented security design, namely ALFSR PUF, that requires small area and less authentication time, as well as small key storage requirement as compared to the state-of-the-art techniques is presented. The ALFSR is implemented using a reprogrammable integrated circuit platform, FPGA. The PUF design is proposed to protect the entire framework’s intellectual property (IP) from emerging attacks such as reverse engineering, physical tampering, and cloning, and potentially to detect malicious IP alteration hardware attacks.

– The resilience of the proposed ALFSR PUF is evaluated against different ML modeling techniques, including artificial neural network (ANN), k-nearest neighbor (kNN), and kernel support vector machines (KernelSVM).

– Using low-cost encryption with an area-efficient AES, the proposed scheme preserves the system integrity and privacy against emerging attacks targeting wireless charging systems.

The rest of the paper is organized as follows. A brief background is offered in “Background”. The proposed scheme

is presented in “Proposed Lightweight Authentication Scheme”. The network model of the proposed scheme is explained in “Network Model”. The proof of concept for the proposed scheme is demonstrated in “Analysis of the Experimental Results”. Finally, conclusions are drawn in

“Conclusion”.

Background

Related Work

SPUFs are one-way physical functions that exploit manufacturing process variation (MPV) of integrated circuits (ICs) to map a set of input challenges to a unique output response for device authentication and robust secret key generation [27–32]. Due to the minuscule variations during the IC fabrication and manufacturing process, every silicon device has unique distinguishing properties. The CMOS transistors are the basic building blocks of ICs fabricated with different parameters, including transistor gate length and width, doping concentration, voltage threshold, and noise, leading to small and inherently random differences in the IC processing time (delay) known as the manufacturing process variations. When mapped on silicon devices, SPUFs expose and magnify the small random delay caused by MPV and convert it to inherently unique digital signatures. PUFs use a challenge-response mechanism to obtain unique device- specific binary secret keys.

SPUFs have recently emerged as a promising hardware- based security primitive to protect intelligent systems, including consumer electronics and smart grid, against invasive and non-invasive attacks [33, 34]. Such attacks include counterfeit parts in electronics consumer manufacturing, physical tampering and reverse-engineering attacks used by an adversary for design cloning and/or overbidding, detection of fault-injection attacks on SRAM and EEPROM based devices, and detection of malicious circuitry such as hardware Trojans [22–24, 31, 35–44].

A linear feedback shift register (LFSR) is a widely used circuit to implement pseudo-random number generators (PRNGs) [45–47]. An LFSR has a simple implementation, low cost, and high efficiency. A password-based hardware authentication using PUFs (PHAP) has been proposed for chip authentication and secret key generation using LFSR in [48]. In this work, a system that distinguishes between a trusted party and an adversary using a simple user password during authentication is presented. As a disadvantage of this scheme, the output of a pseudo-random LFSR is fed as an input challenge to the PUF design, which makes the whole system vulnerable to ML attacks.

Also, an LFSR can be utilized for encryption of the trans- mitted PUF information (challenges and responses) between

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the reader and tag of an RFID authentication scheme [49]. A pseudo-LFSR PUF, namely (PLPUF), has been proposed in [50] to provide random challenges to a PUF-based authentication scheme which is implemented on 16 Spartan-3A FPGA boards. This design is evaluated for uniqueness in terms of Hamming distance (HD), and reliability in terms of false acceptance rate (FAR) and false rejection rate (FRR).

ML‑Based Modeling Attacks on SPUFs

ML algorithm can be generally classified into supervised learning and unsupervised learning, as shown in Fig. 1 [51–53]. In a supervised learning, a training set of data samples are input to an ML algorithm. The algorithm is trained to predict the variables of a dataset which is known as learning from exemplars. Alternatively, unsupervised learning algorithms utilize a different set of ML algorithms where the correct features are not explicitly provided to the algorithm. The algorithm categorizes features of a given dataset using the feature similarities. Unsupervised learning is typically performed using a statistical approach known as density estimation.

ML modeling attacks can be used as an offensive security tool to model the working input-output behavior of PUFs. In this regard, different ML classifiers are used to model secure hardware and embedded systems, potentially causing seri- ous security and privacy concerns. Also, several techniques have been proposed to mitigate these attack vectors. Accord- ing to a recent study, modeling attacks against lightweight PUF-based schemes for IoT authentication and security are classified into three main categories: (a) ML software- based attacks, (b) side-channel hardware-based attacks at the hardware level, and (c) hybrid ML and side-channel attacks [44]. Even though ML attacks are considered as one of the most successful software-based attacks to clone the behavior of a PUF design, the efficiency and predictability of ML attacks decrease with the increase of the complexity of the PUF design [54, 55]. Therefore, the time needed to model

or clone the PUF behavior would not be feasible for more sophisticated PUF structures.

Side-channel attacks exploit information leakage in terms of variations in certain physical parameters such as leakage current, voltage variations, power consumption, execu- tion time, and electromagnetic emanations to extract secrets from us. Typical side channel attacks include power analysis attack [56], timing attack [57], electromagnetic attack [58], and differential fault analysis and photonic emission attacks [59, 60]. Even though side-channel attacks take advantage of the side channel parameters to model a robust PUF design, it is often difficult for these attacks to obtain a sufficiently accurate PUF model. To enhance the modeling time of ML attacks and improve the accuracy of side-channel attacks, recent research proposes to use hybrid (software-based/

hardware-based) cyberattacks that apply the side channel parameters as inputs to ML algorithms to enhance both the PUF modeling time and accuracy [61].

Proposed Lightweight Authentication Scheme

SPUFs can be categorized as weak and strong based on the entropy of the corresponding CRPs [27, 28, 31, 32]. Strong PUFs have a relatively sizeable CRP space which makes these PUF more robust against modeling [27–32]. Alter- natively, a weak PUF can only generate a limited number of CRPs, and thus, they seem to be more vulnerable to ML and modeling attacks. An adversary cannot quickly build an accurate model of a strong PUF after monitoring a large number of CRPs [27–32]. However, obtaining even a small subset of CRPs from a weak PUF can be significantly more difficult as weak PUFs typically utilize their CRPs internally, are typically not given externally.

One primary concern regarding SPUFs is their vulnerability to emerging physical and ML modeling attacks [25, 26]. Different ML-based modeling attacks are being used to uncover the patterns in a SPUF by correlating its response pairs (CRPs). One example of strong PUF is the Arbiter PUF (APUF) that is shown in Fig. 2. An Arbiter PUF is a popular and robust delay-based sPUF known [62]. As shown in the ML algorithm

Unsupervised Learning

Supervised Learning Regression Classification

Clustering

Fig. 1 Brief overview of ML techniques

1 0

D Q

C[0] C[1] C[C-1]

RESPONSE

Challenge Stimulus

Fig. 2 Arbiter PUF (APUF) circuitry [46]

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figure, an APUF circuitry contains a D flip-flop that connects two delay paths; one path connects to the DFF clock signal, and the other connects to the input data signal. The DFF arbiter determines which one of the two racing signals wins and reaches the DFF arbiter’s end first. As shown in Fig. 2, an APUF employs dedicated multiplexers with an input challenge to configure and control the racing path for each PUF response bit.

A ring oscillator (RO) PUF (ROPUF) is a weak delay based PUF [27]. ROPUFs use identically constructed ROs;

each RO has a slightly different frequency due to the unique MPV variations, eventually resulting in random PUF outputs [63–69]. A simple ROPUF circuitry with three inverter stages is shown in Fig. 3 where the architecture of each RO has an odd number of inverters and feedback from the RO output to the RO input. ROPUFs are easy to implement and exhibit more extraordinary performance than other SPUFs, including APUFs. An ROPUF uses simple logic, including multiplexers, counters, and comparators to convert the individual RO frequencies to digital or binary secret keys.

Due to the simple routing requirements, ROPUFs can eas- ily be fabricated using a simple hard-macro procedure. This procedure can guarantee symmetrical RO loops and ensure the extraction of truly random RO frequencies under random process variations.

Consequently, both ROPUFs and APUFs are considered to be suitable for hardware security solutions for authentication in both FPGAs and ASICs. In this paper, we propose a robust hybrid PUF-based authentication scheme that employs a simple LFSR, dedicated muxes, and arbiter D flip flop to improve the PUF security against ML attacks.

More specifically, we propose an ALFSR PUF that applies a one-way irreversible challenge (C) on a physical function to generate a unique and reliable response. The proposed design takes advantage of both the design simplicity of an ROPUF and the strength of an APUF to enhance the security of the proposed framework against modeling attacks.

The proposed PUF design offers a straightforward and lightweight implementation for hardware assisted security

for device authentication and secure key generation. This design occupies a low area and consumes low power, and thus, suitable for extremely energy constrained smart grid applications that can only house low-cost and lightweight hardware assisted security. The proposed scheme is developed to protect the PUF design against ML attacks using low-cost AES encryption. We validated the resilience of our proposed low-cost PUF authentication scheme against many ML algorithms that can be mounted to attack datasets (PUF challenge and response) and propose lightweight encryption against them. Furthermore, the proposed PUF naturally provides protection against physical attacks including physical tampering and cloning.

A high level schematic of the proposed ALFSR PUF instance is shown in Fig. 4. The architecture of proposed framework circuity for the generation of authentication keys (64-bits) and encryption keys (64-bits) are depicted in Fig. 5.

Each block instantiates m identical LFSR instances in one area of the FPGA chip. These instances are easy to realize in different silicon environments such as ASICs and FPGAs and can generate high-performance chip-specific IDs that are highly difficult (almost impossible) to retrieve or clone. The LFSR PUF exploits different parameters such as gate length, threshold voltage, and the non-uniform density of the impu- rity, without controlling the inherently random manufacturing process. LFSR PUF responses are straightforward to generate based on the process variation of the LFSR latches.

The block circuitry of the proposed hybrid lightweight ALFSR PUF design is shown in Fig. 4. The core component of this design is the lightweight LFSR structure. One set of LFSR-based structure is used, as shown in the same color.

Each LFSR structure acts as an RO and generates a unique LFSR frequency. All LFSR structures are connected to two multiplexers MUX1 or MUX2 [42]. These dedicated multiplexers connect the LFSR structures to an arbitrator DFF by applying the input challenges to each multiplexer and the proposed ALFSR design generates a 128-bit output response. A total of 128 LFSR instances are therefore required. Using the same set of 128 LFSR structures will eliminate the need for two separate groups of 128 LFSR structures, allowing for a more area-efficient design to reduce the area and power consumption when implemented on real hardware (FPGAs).

As shown in Fig. 4, the dedicated multiplexers select two LFSR instances based on the applied input challenges and connect them to the D-flip flop clock (Clk) signal and data (D) input signal.

When a new input challenge is applied to the ALFSR PUF design, the arbitrator updates the outputs accordingly, and a new bit is generated as part of the device-unique cryptographic key.

To generate a single response bit (output), two LFSR PUF instances are selected using a challengei and challengej . As

1

2

M

COMPARATOR

Input Challenge (i) M oscillators

Output PUF key (response) 0 or 1 MUX 1MUX 2

Counter 1

Counter 2 Input

Challenge (j)

Input Challenge

Fig. 3 Ring oscillator PUF (ROPUF) circuitry [16]

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Fig. 4 Proposed ALFSR PUF block circuit

D Q

Output RESPONSE

PUF Key

Challenge(i)

FPGACLK

D Q

D Q D Q

D Q

D Q D Q

Arbiter D Flip Flop FPGACLK

D Q

D Q D Q

MU X1

MU X2

Challenge(j)

FPGACLK

LFSR M structures

Fig. 5 Architecture of the proposed authentication scheme

4 x1 Multiplier 128-bit LFSR PUF

Block

128-bit LFSR PUF Block

The generation of PUF-based authentication keys

4 x1 Multiplier 128-bit LFSR PUF

Block

128-bit LFSR PUF Block

The generation of PUF-based encryption keys

Initial permutation (IP) register (128 bits) 128-bits

authentication key (plain text)128

64

2 x1 (64-bit wide) Multiplier 2 x1 (64-bit wide)

Multiplier

AES Round Function

64 64

128 bits

64 64

Encryption Key Processing

64

output validers (OV2)

register (64-bits) output validers (OV1) register (64-bits)

Final permutation (FP)

32 32

128

128-bits Encryption

key

Controller Unite

Encrypted authentication keys (En register) (128-bit cipher ciphertext)

64 64 64

Load IP

Load En Select

OV2 Select

OV1 S1

S3

S4 EKP

LFSR PUF block implementation Low-cost AES implementation

S0

FPGA Clock

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shown in the Fig. 4, a 3-bit asynchronous LFSR circuit is mapped in one slice.

When the G and GE signals are triggered, each latch simply shifts the stored data ‘Q’ to the input of the next latch. For a proper oscillation (non-zero LFSR state), the LFRS is initialized (i.e., power-up states) with a seed value of ‘010’. Every time the ALFSR PUF design compares two frequencies ( f_i and f_j ) obtained by two binary counters, a one-bit output (‘0’ or ‘1’) is generated. The proposed design is implemented on an Artix 7 Xilinx FPGA development board which consists of 5200 slices. Using VHDL language, Xilinx software, and CAD tools, we precisely mapped one instance in one slice of the LFSR PUF using macros design on each FPGA board. In the Artix 7 Xilinx FPGA, each slice contains four 6-input LUTs and four flip-flops.

The architecture of the proposed authentication scheme is shown in Fig. 5. To generate the authentication keys, four identical blocks of the LFSR design are mapped on different areas of the Artix 7 FPGA. These blocks are connected to a 4×1 multiplexer to select one block for the generation of the authentication keys. Since there are n=128 LFSR instances, n² possible authentication keys, each with 128- bits are generated from each block. The previous analogy also applies to the generation of PUF-based encryption keys.

The PUF-based encryption keys are generated similar to the authentication keys.

The AES round function is mapped on the bottom area of Artix-7 FPGA, as shown in Fig. 6. AES implements permutation, a simple Feistel Network round function, and substitution to transform 128-bit plaintext (PUF-based authentication keys) using the 128-bit PUF-based encryption keys [73]. The initial permutation is performed by swapping the input (plaintext), which will not require additional hardware. The final permutation is the inverse of the initial permutation, and the AES algorithm does not require any

extra hardware or logic component to perform this simple operation. The data (authentication keys) input to the Feistel Network round function goes initially through an expansion block before being XORed with a sub encryption key. The output of the XOR function is mapped to the related S-boxes within the AES algorithm. The generated PUF-based keys are not stored on any medium and generated on-demand by the LFSR PUF. These keys are therefore not vulnerable to conventional physical attacks.

As shown in Fig. 5, the AES algorithm implements a low-cost one-round authentication and encryption processing. For each round of AES encryption, a different subkey is used as the round key, produced by the key schedule [73]. A key schedule algorithm (with dedicated hardware) is implemented as a part of the encryption key processing unit to produce the subkeys of the 128-bits PUF-based encryption keys in real-time. The key scheduling is implemented within a key processing unit and controlled by the same control unit. Two 2 × 1 multiplexers (64 bit wide) are used to control the inputs to each round. These two multiplexers initially select the permutation input (new 128-bits authentication keys) stored in a 128-bits shift register. The multiplexers then select the 64-bit output of the previous round and feed it as an input to the next round. The next step is a simple permutation, and finally, the resulting data is XORed with the left part of the initial input data [73]. The output of each round is stored in two output registers (OV1 and OV2) after the final permutation (special AES operation) is performed on them, as shown in Fig. 5. The output register is a low-cost intermediate register to store the output of each round before they are fed back as a new input to the next round. Finally, the final permutation is performed, and the encrypted cipher keys are stored in a 128-bit register.

Network Model

The proposed authentication scheme has three main enti- ties, a utility center charging controller (UCCC), charging stations (CSS), and authenticator’s cloud server, as shown in Fig. 7. First, a PEV customer registers with a UCCC. The UCCC provides the PEV customer with a wireless reprogrammable smart device that implements the proposed authentication scheme for the registration process. This intelligent device implements different instances of an ALFSR PUF and maps the algorithm of a low-cost AES encryption.

The PUF generates a set of authentication keys (128-bits) and another set of encryption keys (128-bits) to encrypt the authentication keys. This UCCC stores all of the possible PUF-based authentication keys (128-bits) encrypted using a lightweight AES that uses PUF-based 128-bits encryption keys. The encrypted PUF-based authentication keys in

Fig. 6 Mapping the AES round function at the bottom area of the FPGA

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UCCC are uploaded to a secure cloud server database when an account is registered with the UCCC.

The details of the proposed implementation and secret key generation are presented in the next section. The registered PEVs use the PUF to generate the authentication and encryption keys in real-time without storing the secret keys.

The authentication keys are encrypted to preserve integrity and confidentiality. The encrypted keys generated by PEVs are sent to an authenticator to perform the matching over encrypted cloud data to authenticate the PEVs at the CS. If the authentication keys sent by the CS match the ones stored at the cloud server, the server sends a positive acknowledg- ment to the CS, verifying the legitimately of the PEV user.

Otherwise, the server sends a negative authorization to deny access to a non-authorized PEV, as shown in Fig. 7. The device is equipped with a wireless connection (WiFi) to exchange information with the CS and has firmware to support the exchange of the authentication key. The authenticator cannot link the authentication request (IDs) sent from an ESU smart chip to preserve privacy.

Analysis of the Experimental Results

The security of the proposed authentication scheme is evaluated using normality, uniqueness, and reliability in “Secu- rity Evaluation of the Proposed Authentication Scheme” and the performance thereof is presented in terms of timing and storage requirements as well as the resilience against ML modeling attacks in “Performance Analysis of the Proposed Authentication Scheme”.

Security Evaluation of the Proposed Authentication Scheme

Normality

According to the central limit theorem (CLT), a normal distribution with sufficiently large sample space exhibits true randomness and is uniformly distributed. The normality of data samples is the foundation of the majority of statistical analysis techniques, including randomness. To assess the normality of the LFSR sample frequencies, a quantile–quantile plot (Q-Q plot) can be used [65]. A Q-Q plot is a typical graphi- cal illustration to indicate the exact normality of data samples by comparing an empirical cumulative distribution function of a variable (LFSR sample frequencies distribution) with a specific theoretical cumulative distribution function (normal

Fig. 7 Network model and mes- sage exchanges for the proposed wireless charging coordination system (WCCS) authentication scheme. Note each smart PEV consists of a smart chip (programmable FPGA chip) that implements lightweight PUF and low-cost AES encryption

Cloud Servers

PEVs community with wireless smart authentication chip

Charging Station (CS1) community Utility center

charging controller (UCCC) Distributed and secure (encrypted)

data cloud database servers (the authenticator data base)

Encrypted PUF keys

(7) Access (deny/allow)

(8) Access (deny/allow)

(5) Search over encrypted PUF-based keys (6) Verification decision (deny/allow)

(2) Uploading the encrypted keys in the secure and distributed cloud data base

(1) PEVs registration and smart chip distribution (4) Encrypted

Authentication keys

(3) Encrypted Authentication

keys

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distribution). [65]. A Q-Q plot for the LFSR data frequencies at varying temperatures, as shown in Figs. 8, 9, 10 and 11, illustrates the correlation between the expected and observed cumulative probabilities (F(fi), G(i)), which can be written as [65]

When a distribution function falls on a straight line (approximately linear), the results follow a normal distribution. As shown in Figs. 8, 9, 10 and 11, LFSR frequencies under different temperatures follow almost the same trend, which typically does not entirely lie on a straight normality line. This behavior illustrates that the temperature variation has uniformly impacted the average RO frequencies in a similar fashion. This is actually the desired behavior demonstrating the normality of the proposed PUF.

Uniqueness

One of the essential quality metrics for a PUF design is the uniqueness of the generated output. PUF uniqueness test characterizes the way digital signatures are generated after implementing the same PUF design on different silicon devices. For n PUF responses (secret keys), the average PUF uniqueness is determined using the average value of the calculated HD among different PUF responses. An HD between two PUF responses from two different devices is produced by comparing each bit in one response with the corresponding bit in the other response. The distribution of HD values is then determined using the obtained HDs, (1) F(f_i) =P(f <i),

G(i) = (2) i− ¹

2

n .

Fig. 8 Normal Q-Q Plots for the average LFSR frequencies at 20 ^◦C

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which is also known as the inter-die HD distribution. The ideal average HD value is 0.5 [63, 64]. Having an average uniqueness value close to 0.5 indicates that any response generated by implementing PUF on a certain device is truly random and uniquely independent from any other response generated by implementing the same PUF on different devices. PUF responses can be seen as random sets with a 50% probability of having 0 and a 50% likelihood of having 1 for each response.

PUF uniqueness is calculated using inter-die HD for Spar- tan 2, and Spartan 3E FPGA devices by [27, 42]

where u and v are two devices, R_u and R_v are, respectively, the response vectors of u and v chips, n is the number of PUF instances, and m is the number of FPGAs. Ideally, the PUF responses should only depend on the random process variations independent of PUF locations [42]. To generate a PUF signature, neighbor coding selection is used [27, 32, 42]. We used L = 129 frequencies to generate 128-bits response. As shown in Fig. 12, the number of binary comparison performed to calculate the PUF uniqueness using 30 FPGA chips, is N = C₂ⁿ = 435 comparisons, where n = 30 devices with an average PUF uniqueness of U = 50.56

% and standard deviation of 𝛿 = 1.31 are used. The uniqueness result demonstrates that the proposed ALFSR PUF is a robust hardware-based design that can be utilized to generate inertly unique secret keys for cryptographic applications [42, 74].

(3) U= 2

m(m−1)

m−1

∑

u=1 m

∑

v=u+1

HD(R_u, R_v) n ,

Reliability

Reliability measures the consistency of a PUF structure in generating the same response bits using the same RO pair under temperature variations. The ideal reliability value is 100% [63–65, 74]. To evaluate the reliability of a PUF, the FPGAs-under-test are placed in a temperature chamber to control the environmental temperature. The PUF responses are obtained at various temperatures and compared to the responses generated at room temperature (RT) with a logic analyzer.

PUF responses are generated using neighbor coding selection, and LFSR frequencies are compared to the neigh- boring CLBs. The reliability results of 128 bits obtained from the ALFSR PUF mapped on 10 FPGAs at four different temperatures are shown in Fig. 13. The results show that our average PUF reliability is 97.9% and there is 2.67 bit flips, out of 128 bits, at At 20 ^◦ C. These values represent the highest PUF reliability with the lowest bit flip rate, as shown in Fig. 13. At 40 ^◦ C, the average reliability reduces slightly to 96.3%, with 4.74 bit flips out of 128 bits. As the temperature increases to 60 ^◦ C, the average reliability decreases to 95.1%, with 6.27 bit flips out of 128 bits, representing the lowest reliability with the highest bit flip rate. When the temperature is increased to 80 ^◦ C, the reliability slightly improves to 95.4%, with 5.12 bit flips out of 128 bits, representing the second-lowest reliability with the second-lowest bit flip rate. The overall observation is that the temperature variations slightly impact the PUF reliability as the temperature deviates from the RT.

Performance Analysis of the Proposed Authentication Scheme

Timing and Latency Analysis

In a fully pipelined architecture, a new plaintext can be encrypted in each clock cycle. A fully pipelined architecture

120

100

80

60

40

20

0 4 .50 4 .00 4 5 . 5 .50 5 .00

=

Mean= .56 Std.

Dev. = 1. 1

Frequency

HDs

Fig. 12 ALFSR PUF uniqueness test results

20⁰C 40⁰C 80⁰C

85 90 95 100

60⁰C

Temperature

Reliability Average%

Fig. 13 ALFSR PUF reliability test results

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is suitable for high-performance computing (i.e., high throughput) where the design cost is not a significant con- straint. Alternatively, the round-based implementation proposed in this paper provides the lowest area and is suitable for resource-constrained applications. To improve the speed, the generation and the encryption processes can be overlapped so that while the encryption is being performed, the next key can be generated simultaneously. This can be man- aged by a control unit and reduces the time of total clock cycles for every new key generation. Regardless of the speed of encryption (as it is assumed to be not critical here), the ultimate goal in this work is to achieve hardware-assisted security that has low power and area overhead with a com- parably less complex design.

Five security levels (L1–L5) are proposed by the National Institute of Standards and Technology (NIST) that can be applied to realize a fully secure authentication system [70, 71]. Accordingly, the total real-time required for the encryption of the authentication keys using our proposed technique is analyzed for all five NIST security levels (i.e., second (128-bits), third (256-bits), fourth (512-bits), and fifth (1024-bits) levels). The encryption time is quite short and can be overlapped with the generation time. According to the implementation, the generation of one bit from the authentication and encrypted key simultaneously takes 0.01 ms.

The total authentication and encryption time for a 128- bits key is 0.01 × 128 = 1.28 ms, at real time. Assuming that a car needs to charge once every day, the L1 authentication process is performed 365 times per year, requiring a total real-time generation and encryption time of 365×1.28 ms=

0.47 s within a year. For a 10-years lifespan, the proposed authentication scheme needs a total of 4.67 s for the L1 authentication level. For a period of 10-years, if L1 requires 4.67 s, L2 requires 9.34 s (4.67 × 2), L3 requires 18.68 s (9.34 × 2), L4 requires 37.36 s (18.68 × 2), and L5 requires 74.72 s (37.36 × 2).

Storage Requirements

The storage requirement for the authentication levels of the proposed scheme according to NIST standards is also explored in this section. For L1, the authentication process is performed where 128 different authentication bits are encrypted and sent every time a PEV needs to authenticate itself to the UCCC [34]. For a community of 200 vehicles, an external hard drive with a size of 25,600 bits = 3.12 kB (128× 200) is required to store the encrypted PUF secret key information in terms of encrypted binary PUF response bits. Assuming that a car needs to be charged twice a week, every week, 200 cars would require 200 × 2 × 3.12 = 1248 KB= 1.25 MB. For one year, this car community would need (1.25 × 4 × 12 = 60 MB. For a 10-years lifespan, the proposed scheme needs a total size of 600 MB to store all of the

authentication keys required per L1. Accordingly, for period of 10 year, L2 requires 1200 MB (2 × 60), L3 requires 2.34 GB (2 × 1200 MB) , L4 requires 4.68 GB (2 × 2.34 GB), and L5 requires 9.36 GB (2 × 4.68 GB), with a total storage area of around 18.1 GB.

Resilience of ALFSR PUF Against ML Modeling Attacks

In this work, three supervised ML algorithms, namely ANN, kNN, and kernelSVM, are studied to investigate the resilience of the ALSFR PUF against ML modeling attacks. The algorithms are trained using different testing and training datasets, and the results are analyzed to determine the best ML model that is able to clone the PUF with the highest prediction accuracy.

ANN‑Based Modelling

The proposed authentication scheme for smart PEVs applications requires two communication phases between the two parties (smart PEVs and charging stations). This communication adds a series of security challenges with an increased computational cost. ANNs are known for their applications in modeling relationships that possess a high degree of non-linearity between modeling inputs and outputs. ANN is therefore used to model the proposed ALFSR and can have major impacts on the security of the proposed authentication scheme. ANN is an intelligent adaptive system that mainly consists of interconnected hidden neurons (ANN nodes) to support the computation performed by these layers. The ANN structure can be a simple, single-layer per- ceptron (SLP) that contains one layer of hidden neurons.

The main drawback of an SLP structure is its incapability to efficiently deal with linearly separable data. To solve this issue, a more structured and advanced ANN is used to deal with the non-linear data, known as a multi-layer percep- tron (MLP). In ANN, the information of a training dataset is used as an input to the algorithm. For each input neuron, the information is used to calculate a biased weight before these weights are accumulated and fed to a function called the activation function.

Gaussian radial basis function (RBF) ANN approach is considered to improve the neural network model accuracy to model the PUF behavior without increasing the complexity degree of the network, as seen in Fig. 14 [72]. The Gaussian RBF is utilized to model the CRP behavior of the proposed PUF design. In Gaussian RBF, we evaluate the ability of ANN to break the PUF design by attempting to model the CRP behaviors. As shown in Fig. 15, a three hidden layer model of ANN is used where the CRPs are set as the input variables while the response bits are set as outputs. A typical

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radial function is the Gaussian which, in the case of a scalar input, can be written as

where c represents Gaussian RBF center and r is its radius.

The accuracy results after training the ANN model with different number of CRPs are shown in Fig. 16. As the number of CRPs decrease from 10,000 to 1000, the accuracy of the model decreases from around 77% to less than 65%.

The model is trained using 70% training dataset and 30%

testing dataset.

Support Vector Machine (SVM)

Support vector machine (SVM) is a popular ML classifier suitable for linear and nonlinear binary classification.

The learning of the support vector depends on the inner mapping functions known as kernels. For the comparison, the RBF classifier is also used with the SVM approaches, which use the Gaussian formula to map the data samples to a higher dimensional space and to create a nonlinear class separation. To evaluate the ALFSR PUF immunity against ML attacks, RBF SVM is used to model the CRPs of our ALFSR PUF. In this regard, it is assumed that the attacker can first hack into the scheme and have knowledge regarding part of the CRP information used in the system to obtain PUF-based authentication keys.

SVM is suitable for PUF modeling since the CRPs are binary data (‘1’ and ‘0’). In this respect, the SVM classi- fies these datasets by learning the best hyperplane, with the most significant margin between two classes, to separate two types. Alternatively, the SVM classifier aims to find an optimal hyperplane separation between two classes (4) h(x) =exp−

[(x−c)² r²

] ,

Fig. 14 Overview of ML techniques using RPF classifier [72]

Fig. 15 The proposed ANN ML technique

Fig. 16 Accuracy results of ML modeling using ANN technique

Fig. 17 Accuracy results of ML modeling using SVM technique

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by increasing the margin between the class points. The SVM is trained using X datasets (input challenges) with a Y classifier (output responses). X and Y are given to the Gaussian RBF train function to train the SVM classifier that uses a scaling factor sigma for the training. Different number of CRPs ranging from 10,000 to 1000 is used.

The accuracy results after training the SVM model with different number of CRPs are shown in Fig. 17. As the number of CRPs decrease from 10,000 to 1000, the accuracy of the model decreases from around 65% to less than 60%. The model is trained using 70% training dataset and 30% testing dataset.

k‑Nearest Neighbors (kNN)

kNN is a widely used and simple ML classifier, which is based on a supervised learning paradigm and regressive method for pattern recognition. kNN is generally used in the case of dataset where there is no prior knowledge of the distribution of the dataset. kNN uses the entire data during the training phase, and the model trains the K number of neighbors. The more the number of neighbors each node has, the more accurately this team of neighbors can determine correct predictions. However, too many neighbors would

cause overfitting on the training set, and the predictions will lack new observations in the dataset.

In ML modeling, many metrics are used to evaluate the performance of the ML classifier. The confusion matrix is one of the metrics that use an n×n matrix, where ‘n’ is the number of class labels to evaluate the performance of the kNN algorithm. Figure 18 demonstrates the kNN performance using confusion matrix where the model accuracy is around 77.67% and the model is trained on 75% of the dataset and tested on 25% of the dataset. There are four possible values in the confusion matrix, true positives (TP) known as positives that are correctly predicted, true negatives (TN)

Table 1 Comparison of average accuracy of ML ALFSR PUF modeling with 10,000 CRPs

Algorithm Number of CRPs Xtest (%) Xtrain (%) Model accuracy (%)

Test error (%) Average accuracy (%)

ANN 10,000 0.15 0.85 95.10 4.90 93.40

0.25 0.75 91.90 8.10

0.35 0.65 93.20 6.80

SVM 0.15 0.85 79.90 20.10 79.50

0.25 0.75 79.80 20.20

0.35 0.65 78.90 21.10

kNN 0.15 0.85 59.90 40.10 61.30

0.25 0.75 61.20 38.80

0.35 0.65 62.70 37.30

TP = 270 FN = 79

FP = 61 TN =220

Fig. 18 Accuracy results of kNN ML modeling technique

Fig. 19 Comparison accuracy results between ML techniques with different datasets

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known as the negatives that are correctly predicted, false positives (FP) are the negatives which are predicted as positive, and false negatives (FN) are the positives which are predicted as negative [75].

The accuracy of kNN, A(kNN), can be determined as

For a more complete accuracy comparison, the ANN model is also trained using different sizes of training (Xtrain) and testing datasets (Xtest). As tabulated in Table 1, the ANN ML classifier is trained using 65%, 75%, and 85% of the dataset and tested using 35%, 25%, and 15% of the dataset, respectively. The results are compared with SVM and kNN classifiers, as shown in Fig. 19. With different training and testing dataset sizes, the ANN has the highest average accuracy, higher than 93.4%, the SVM has an accuracy value close to 79.5%, and kNN has the lowest accuracy which is on average less than 61.3%. This indicates that the proposed ALFSR PUF framework is more vulnerable to ANN attacks and more resilient to potential SVM and kNN ML attacks launched by an adversary.

Conclusion

A proof of concept for the hardware-assisted framework for secure and trusted plug-in electric vehicle (PEV) charging coordination technology using lightweight LFSR-based PUF and low-cost data encryption is proposed in this paper. The proposed framework is implemented on FPGAs. The article covers the authentication protocol between the utility center charging controller and a cloud-based authenticator. The hardware-based identities are encrypted using a low-cost AES encryption technique to ensure integrity and confidentiality. The experimental results demonstrate that the proposed framework is efficient, trusted, and highly secure. The proposed scheme exhibits an average uniqueness of 50.55%

when implemented in 30 FPGA devices. The experimental results demonstrate that the framework is reliable under temperature variations–the average reliability value ranges from 95.1 to 97.9%, with a competitively low bit flip per- centage. Finally, the proposed ALFSR PUF framework for ESUs security is more vulnerable to ANN attacks and more resilient to potential SVM and kNN ML attacks launched by an adversary. Using low-cost encryption within area-efficient AES, the proposed scheme preserves the system integrity and privacy against possible ML attacks targeting the wireless charging systems.

Acknowledgements This work is supported in part by the NSF Award under Grant CNS-1929774.

(5) A(kNN) = TP+TN

TP+FN+TN+FP.

Declarations

Conflict of interest On behalf of all authors, the corresponding author states that there is no conflict of interest.

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