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Program Specification: Master of Electrical and Microsystems Engineering V6M: Multi-processor and Multi-core Designs for Reliable Embedded Systems Learning Objectives:

This module considers the challenges involved in creating distributed (multi-processor) designs and the related challenges involved with multi-core (“Network on Chip”) designs.

This module considers the challenges involved in creating distributed (multi-processor) designs and the related challenges involved with multi-core (“Network on Chip”) designs. The module also covers key issues such as: Assigning tasks to processors / cores; Clock synchronisation; Suitable communication protocols; Ensuring reliable data transfers; Using multiple processor cores to enhance fault tolerance.

Previous Experience/Premise none

Content:

Topic 1:

A review of a single core design

 datapath,

 pipelining, and

 cache design

Topic 2:

Multi-core COTS Processor

 Improving performance.

 Multi-processor vs. multi-core: similarities and differences.

 Maintaining design integrity when migrating from a single-processor solution.

 Improving reliability.

 Creating an “event processor”. Avoiding resource conflicts in multi-core designs.

Topic 3:

 Introduction to OpenMp programming and MPI Topic 4:

Design Challenges

 Scheduling issues.

 Maintenance.

 Adapting task sets for distributed systems. Example automotive control system.

Topic 5:

Timing Issues

 Impact of jitter.

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 Different forms of clock synchronisation algorithm. Assessing what happens when something goes wrong.

 Timing in the event of errors Topic 6:

Controller Area Network (CAN) Protocol

• Creating a simple multi-processor design using CAN.

• Challenges of clock synchronisation.

• Timing of tasks and network communications.

• Basic use of watchdogs.

• Running without clock synchronisation.

Topic 7:

Improving Reliability in Distributed Designs

• Adding redundant Master nodes.

• Adding redundant Slave nodes.

• Hot standbys.

• Adding redundant communication paths. Bus vs. star topologies.

• Compare performance of different architectures.

• Safety Integrity Levels.

Teaching session: Block seminar (two weeks) Credit Points: 5 CP according to ECTS

Lecturer: Prof. Dr. Yap (Universiti Tunku Abdul Rahman Frequency: Every year

Referenzen

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