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GA34-0152-0 File No. Sl-01

IBM Series/1

Principles of Operation

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File No. S1-01

IBM Series/1

Principles of Operation

Series/1

First Edition (April 1981)

Use this publication only for the purpose stated in the Preface.

Changes are periodically made to the information herein; any such changes will be reported in subsequent revisions or Technical Newsletters.

It is possible that this material may contain reference to, or information about, IBM products (machines and programs), programming, or services that are not announced in your country.

Such references or information must not be construed to mean that IBM intends to announce such IBM products, programming, or services in your country.

Publications are not stocked at the address given below. Requests for copies of IBM publica- tions should be made to your IBM representative or the IBM branch office serving your locality.

This publication could contain technical inaccuracies or typographical errors. A form for readers' comments is provided at the back of this publication. If the form has been removed, address your comments to IBM Corporation, Information Development, Department 27T, P.O. Box 1328, Boca Raton, Florida 33432. IBM may use and distribute any of the informa- tion you supply in any way it believes appropriate without incurring any obligation whatever.

You may, of course, continue to use the information you supply.

© Copyright International Business Machines Corporation 1981

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This publication describes the common functional characteristics of IBM Series/1 processors and their optional features.

Th~ reader should understand data processing terminology and be familiar with binary and hexadecimal numbering systems.

This publication is intended primarily as a reference manual for experienced programmers who require machine code information to plan, correct, and modify programs written in the assembler language. It is also intended for the person who requires machine status information and interrupt-handling procedures.

This manual is to be used in conjunction with Series/1 processor and I/O description manuals.

Chapter 1. Introduction is an introduction to the Series/I. It contains a general description of the processors and features.

Chapter 2. Processor Unit Description contains a description of processor hardware, including registers and indicators.

Main storage data formats and addressing are presented in this chapter.

The "Program Execution" section covers:

• Basic instruction formats

• Effective-address generation

• Processor state control

• Initial program load (IPL) Jumping and branching

• Level switching and interrupts

• Stack operations

Chapter 3. Interrupts and Level Switching describes the priority interrupt levels and the interrupt processing for I/O devices and class interrupts. Related topics are:

Program-controlled level switching Interrupt masking facilities

Recovery from error conditions

Preface

Chapter 4. Input/Output Operations describes the I/O commands and control words that are used to operate the I/O devices. Condition codes and status information relative to the I/O operation are also explained. Specific command and

status-word bit structures are contained in the I/O device description manuals.

Chapter 5. Storage Address Relocation Translator describes the relocation translator, including relocation addressing and address space management. The storage address relocation translator is not available on some processors.

Chapter 6. Clock/Comparator explains the functions of the clock/comparator. The clock/ comparator is not available on some processors.

Chapter 7. Floating-Point Feature describes the optional floating-point feature.' The floating-point feature is not available for some processors.

Chapter 8. Instructions describes the basic instruction set, including indicator settings and possible exception conditions. Individual instruction word formats that contain bit

combinations for the operation codes and function fields are included. The instructions are arranged in alphabetical sequence based on assembler mnemonics.

Appendixes:

• Instruction formats

• Assembler syntax

• Number systems and conversion tables

• Character codes

• Carry and overflow indicators

• Reference information

Note: Refer to individua1 processor publications for a discussion of the optional programmer console.

Related Publications

Additional publications are listed in the IBM Series/1 Graphic Bibliography, GA34-0055.

Preface iii

iv GA34-0152

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Chapter 1. Introduction 1-1 Processor Characteristics 1-1 Processor Description 1-1

Input/Output Units, I/O Features, and Processor Options 1-3

Chapter 2. Processor Unit Description 2-1 Main Storage 2-1

Addressing Main Storage 2-1 Arithmetic and Logic Unit (ALU) 2-2 Numbering Representation 2-3 Registers 2-5

System Registers 2-6 Level Registers 2-8 Indicator Bits 2-9

Even, Negative, and Zero Result Indicators 2-10 Even, Carry, and Overflow Indicators-Condition Code

for Input/Output Operations 2-10

Carry and Overflow Indicators-Add and Subtract Operations 2-10

Carry and Overflow hldicators-Shift Operations 2-11

Indicators-Compare Operations 2-11 Indicators-Multiple Word Operands 2-14 Testing Indicators with Conditional Branch and Jump

Instructions 2-15 Supervisor State Bit 2-15 In-Process Bit 2-16 Trace Bit 2-16

Summary Mask Bit 2-16 Program Execution 2-16

Instruction Formats 2-16

Effective-Address Generation 2-21 Processor State Control 2-30 Initial Program Load (IPL) 2-33 Sequential Instruction Execution 2-34 Jumping and Branching 2-34 Level Switching and Interrupts 2-35 Stack Operations 2-35

Chapter 3. Interrupts and Level Switching 3-1 Interrupt Scheme 3-2

Level Status Block (LSB) 3-3 Automatic Interrupt Branching 3-3 I/O Interrupts 3-5

Prepare I/O Device for Interrupt 3-5 Present and Accept I/O Interrupt 3-6 Class Interrupts 3-9

Priority of Class Interrupts 3-10 Present and Accept Class Interrupt 3-11 Recovery Procedures for Class Interrupts 3-17

Machine Check 3-17 Program Check 3-18

Power/Thermal Warning 3-18 Supervisor Call 3-18

Soft-Exception Trap 3-19 Trace 3-19

Contents

Clock 3-19 Console 3-19

Processor Status Word 3-20 Interrupt Masking Facilities 3-24

Summary Mask 3-24

Interrupt Level Mask Register 3-25 Device Mask (I-Bit) 3-25

Program-Controlled Level Switching 3-26 Selected Level Lower Than Current Leval and

In-Process Bit On 3-27

Selected Level Equal to Current Level and In-Process Bit On 3-27

Selected Level Higher Than Current Level and In-Process Bit On 3-27

Selected Level Lower Than Current Level and In-Process Bit Off 3-28

Selected Level Equal to Current Level and In-Process Bit Off 3-28

Selected Level Higher Than Current Level and In-Process Bit Off 3-28

Chapter 4. Input/Output Operations 4-1 Operate I/O Instruction 4-2

Immediate Device Control Block (IDCB) 4-3 Device Control Block (DCB) 4-5

I/O Commands 4-7 DPC Operation 4-13 Cycle-Steal 4-15

Start Command 4-16

Start Cycle Steal Status Command 4-20 Cycle-Steal Device Options 4-22

Burst Mode 4-22 Chaining 4-22 Extended DCB 4-23

Program-Controlled Interrupt (PCI) 4-23 Suppress Exception 4-23

I/O Condition Code and Status Information 4-26 I/O Instruction Condition Codes 4-26 Interrupt Condition Codes 4-28 I/O Status Information 4-29

Chapter S. Storage Address Relocation Translator 5-1 Translator Description 5-1

Storage Mapping 5-2 Relocation Addressing 5-2 Storage Protection 5-4

I/O Storage Access Using the Relocation Translator 5-4 Status of Translator After Power Transitions

and Resets 5-4

Error-Recovery Considerations 5-5 Invalid Storage Address 5-5 Protect Check 5-5

Address Space Management 5-6 Active Address Key 5-6

Equate Operand Spaces (EOS) 5-6 Address Space 5-7

Address Key Values After Interrupts 5-9

Contents v

Chapter 6. Clock/Comparator 6-1 Clock/Comparator Features 6-1

Clock 6-1 Comparator 6-2

Chapter 7. Floating-Point Feature 7-1 Data Format 7-1

Number Representation 7-2 Floating-Point Numbers 7-2 Binary Integers in Main Storage 7-3 Normalization 7-3

Programming Considerations 7-3

Floating-Point Feature Not Installed 7-3 Floating-Point Registers 7-4

Arithmetic Indicators 7-4 Floating-Point Exceptions 7-4 Floating-Point Instructions 7-5

Instruction Formats 7-6 Exception Conditions 7-7

Program-Check Conditions 7-7 Soft-Exception Trap Conditions 7-7 Additional Error Information 7-8 Single Precision 7-8

Addition 7-8 Subtraction 7-8 Multiplication 7-9 Division 7-9 Double Precision 7-9

Addition 7-9 Subtraction 7-10 Multiplication 7-tO Division 7 -10 Chapter 8. Instructions 8-1 Add Address (AA) 8-2

Register Immediate Long Format 8-2 Storage Immediate Format 8-2 Add Byte (AB) 8-4

Add Byte Immediate (ABI) 8-5 Add Carry Register (ACY) 8-5 Add Doubleword (AD) 8-6

Register/Storage Format 8-6 Storage/Storage Format 8-7 Add Word (A W) 8-8

Register /Register Format 8-8 Register /Storage Format 8-8 Storage/Register Long Format 8-9 Storage/Storage Format 8-10 Add Word With Carry (AWCY) 8-11 Add Word Immediate (A W) 8-11

Storage Immediate Format 8-12 Branch Unconditional (B) 8-13 Branch and Link (BAL) 8-14 Branch and Link Short (BALS) 8-15 Branch on Condition (BC) 8-16 Branch on Condition Code (BCC) 8-18 Branch on Not Condition (BNC) 8-19 Branch on Not Condition Code (BNCC) 8-21 Branch on Not Overflow (BNOV) 8-22 Branch on Overflow (BOV) 8-23 Branch Indexed Short (BXS) 8-24 Compare Address (CA) 8-25

Register /Immediate Long Format 8-25 Storage Immediate Format 8-25 Compare Byte (CB) 8-27

Register/Storage Format 8-27 vi GA34-0152

Storage/Storage Format 8-27 Compare Byte Immediate (CBI) 8-28 Compare Doubleword (CD) 8-29

Register/Storage Format 8-29 Storage/Storage Format 8-30

Compare Byte Field Equal and Decrement (CFED) Compare Byte Field Equal and Increment (CFEN) Compare Byte Field Not Equal and Decrement

(CFNED) 8-32

Compare Byte Field Not Equal and Increment (CFNEN) 8-32

Complement Register (CMR) 8-33 Copy Address Key Register (CPAKR) 8-33

System Register/Storage Format 8-33 System Register/Register Format 8-34 Copy Current Level (CPCL) 8-35 Copy Clock (CPCLK) 8-35 Copy Comparator (CPCMP) 8-36 Copy Console Data Buffer (CPCON) 8-36 Copy Floating Level Block (CPPLB) 8-37 Copy Interrupt Mask Register (CPIMR) 8-38 Copy In-Process Flags (CPIPF) 8-38 Copy Level Block (CPLB) 8-39

Copy Level Status Register (CPLSR) 8-40 Copy Processor Status and Reset (CPPSR) 8-40 Copy Storage Key (CPSK) 8-41

Copy Segmentation Register (CPSR) 8-42 Compare Word (CW) 8-43

Register /Register Format 8-43 Register /Storage Format 8-43 Storage/Storage Format 8-44 Compare Word Immediate (CWI) 8-45

Register Immediate Long Format 8-45 Storage Immediate Format 8-46 Divide Byte (DB) 8-48

Divide Doubleword (DD) 8-48 Diagnose (DIAG) 8-49 Disable (DIS) 8-49 Divide Word (DW) 8-50 Enable (EN) 8-51 Floating Add (FA) 8-52

Storage/Register Format 8-52 Register /Register Format 8-53 Floating Add Double (FAD) 8-54 Storage/Register Format 8-54 Register/Register Format 8-55 Floating Compare (FC) 8-56

Floating Compare Double (FCD) 8-56 Floating Divide (FD) 8-57

Storage/Register Format 8-57 Register/Register Format 8-58 Floating Divide Double (FDD) 8-59

Storage/Register Format 8-59 Register /Register Format 8-60 Fill Byte Field and Decrement (FFD) 8-61 Fill Byte Field and Increment (FFN) 8-61 Floating Multiply (FM) 8-62

Storage/Register Format 8-62 Register/Register Format 8-63 Floating Multiply Double (FMD) 8-64

Storage/Register Format 8-64 Register/Register Format 8-65 Floating Move (FMV) 8-66

Storage/Register Format 8-66 Register/Storage Format 8-67

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Register/Register Format 8-67 Floating Move and Convert (FMVC) 8-68

Storage/Register Format 8-68 Register/Storage Format 8-69

Floating Move and Convert Double (FMVCD) 8-70 Storage/Register Format 8-70

Register/Storage Format 8-71 Floating Move Double (FMVD) 8-72

Storage/Register Format 8-72 Register/Storage Format 8-72 Register/Register Format 8-73 Floating Subtract (FS) 8-74

Storage/Register Format 8-74 Register/Register Format 8-75 Floating Subtract Double (FSD) 8-76

Storage/Register Format 8-76 Register/Register Format 8-77 Operate I/O (10) 8-78

Interchange Operand Keys (IOPK) 8-79 Interchange Registers (lR) 8-79 Jump Unconditional (J) 8-80 Jump and Link (JAL) 8-80 Jump on Condition (JC) 8-81 Jump on Count (JCT) 8-83 Jump on Not Condition (JNC) 8-84 Level Exit (LEX) 8-86

Load Multiple and Branch (LMB) 8-87 Multiply Byte (MB) 8-88

Multiply Doubleword (MD) 8-89 Move Address (MV A) 8-90

Storage Address to Register Format 8-90 Storage Immediate Format 8-91

Move Byte (MVB) 8-92 Register /Storage Format 8-92 Storage/Storage Format 8-93 Move Byte Immediate (MVBI) 8-94 Move Byte and Zero (MVBZ) 8-94 Move Doubleword (MVD) 8-95

Register/Storage Format 8-95 Storage/Storage Format 8-96

Move Doubleword and Zero (MVDZ) 8-96 Move Byte Field and Decrement (MVFD) 8-97 Move Byte Field and Increment (MVFN) 8-97 Move Word (MVW) 8-98

Register/Register Format 8-98 Register/Storage Format 8-98 Register /Storage Long Format 8-99 Storage/Register Long Format 8-100 Storage/Storage Format 8-100 Move Word Immediate (MVWI) 8-101

Storage/Register Format 8-101 Storage Immediate Format 8-102 Move Word Short (MVWS) 8-103

Register/Storage Format 8-103 Storage/Register Format 8-104 Move Word and Zero (MVWZ) 8-105 Multiply Word (MVW) 8-106 No Operation (NOP) 8-107 AND Word Immediate (NWI) 8-107 OR Byte (OB) 8-108

Register /Storage Format 8-108 Storage/Storage Format 8-109 OR Doubleword (OD) 8-110

Register/Storage Format 8-110 Storage/Storage Format 8-111

OR Word (OW) 8-112

Register/Register Format 8-112 Register/Storage Format 8-112 Storage/Register Long Format 8-113 Storage/Storage Format 8-114 OR Word Immediate (OWl) 8-115

Register Immediate Long Format 8-115 Storage Immediate Format 8-115 Pop Byte (PB) 8-117

Pop Doubleword (PD) 8-117 Push Byte (PSB) 8-118 Push Doubleword (PSD) 8-118 Push Word (PSW) 8-119 Pop Word (PW) 8-119 Reset Bits Byte (RBTB) 8-120

Register/Storage Format 8-120 Storage/Storage Format 8-120 Reset Bits Doubleword (RBTD) 8-122

Register/Storage Format 8-122 Storage/Storage Format 8-123 Reset Bits Word (RBTW) 8-124

Register/Register Format 8-124 Register/Storage Format 8-124 Storage/Register Long Format 8-125 Storage/Storage Format 8-126

Reset Bits Word Immediate (RBTWI) 8-126 Register Immediate Long Format 8-126 Storage Immediate Format 8-127 Subtract Address (SA) 8-128

Register Immediate Long Format 8-128 Storage Immediate Format 8-129 Subtract Byte (SB) 8-130

Set Bits Byte (SBTB) 8-131 Register/Storage Format 8-131 Storage/Storage Format 8-132 Set Bits Doubleword (SBTD) 8-133

Register/Storage Format 8-133 Storage/Storage Format 8-133 Set Bits Word (SBTW) 8-135

Register/Register Format 8-135 Register/Storage Format 8-135 Storage/Register Long Format 8-136 Storage/Storage Format 8-137 Set Bits Word Immediate (SBTWI) 8-137

Register Immediate Long Format 8-137 Storage Immediate Format 8-138 Subtract Carry Indicator (SCY) 8-139 Subtract Doubleword (SD) 8-140

Register/Storage Format 8-140 Storage/Storage Format 8-141 Set Address Key Register (SEAKR) 8-142

System Register/Storage Format 8-142 System Register/Register Format 8-143 Set Clock (SECLK) 8-143

Set Comparator (SECMP) 8-144 Set Console Data Lights (SECON) 8-144 Set Floating Level Block (SEFLB) 8-145 Set Interrupt Mask Register (SEIMR) 8-146 Set Indicators (SEIND) 8-146

Set Level Block (SELB) 8-147 Set Storage Key (SESK) 8-149

Set Segmentation Register (SESR) 8-150

Scan Byte Field Equal and Decrement (SFED) 8-151 Scan. Byte Field Equal and Increment (SFEN) 8-151 Scan Byte Field Not Equal and Decrement

Contents vii

(SFNED) 8-152

Scan Byte Field Not Equal and Increment (SFNEN) 8-152

Shift Left Circular (SLC) 8-153 Immediate Count Format 8-153 Count in Register Format 8-154 Shift Left Circular Double (SLCD) 8-155

Immediate Count Format 8-155 Count in Register Format 8-156 Shift Left Logical (SLL) 8-157

Immediate Count Format 8-157 Count in Register Format 8-157 Shift Left Logical Double (SLLD) 8-158

Immediate Count Format 8-158 Count in Register Format 8-158 Shift Left and Test (SLT) 8-159

Shift Left and Test Double (SLTD) 8-160 Shift Right Arithmetic (SRA) 8-161

Immediate Count Format 8-161 Count in Register Format 8-161

Shift Right Arithmetic Double (SRAD) 8-162 Immediate Count Format 8-162

Count in Register Format 8-162 Shift Right Logical (SRL) 8-163

Immediate Count Format 8-163 Count in Register Format 8-163 Shift Right Logical Double (SRLD) 8-164

Immediate Count Format 8-164 Count in Register Format 8-164 Store Multiple (STM) 8-165 Stop (STOP) 8-165

Supervisor Call (SVC) 8-166 Subtract Word (SW) 8-167

Register/Register Format 8-167 Register/Storage Format 8-167 Storage/Register Long Format 8-168 Storage/Storage Format 8-169 Subtract Word With Carry (SWCY) 8-170 Subtract Word Immediate (SWI) 8-171

Register Immediate Long Format 8-171 Storage Immediate Format 8-172 Test Bit (TBT) 8-173

Test Bit and Reset (TBTR) 8-173 Test Bit and Set (TBTS) 8-174 Test Bit and Invert (TBTV) 8-174

viii GA34-0152

Test Word Immediate (TWI) 8-175 Register Immediate Long Format 8-175 Storage Immediate Format 8-175 Invert Register (VR) 8-176 Exclusive OR Byte (XB) 8-177 Exclusive OR Doubleword (XD) 8-178 Exclusive OR Word (XW) 8-179

Register/Register Format 8-179 Register/Storage Format 8-180 Storage/Register Long Format 8-181 Exclusive OR Word Immediate (XWI) 8-182 Appendix A. Instruction Formats A-I Appendix B. Assembler Syntax B-1 Coding Notes B-1

Legend for Machine-Instruction Operands B-1 Appendix C. Number Systems and Conversion Tables Binary and Hexadecimal Number Systems C-l

Binary Number Systems C-l Hexadecimal Number Systems C-2 Hexadecimal-Decimal Conversion Tables C-4 Appendix D. Character Codes D-l

Appendix E. Carry and Overflow Indicators E-l Carry Indicator Setting E-l

Add Operation Examples E-l Subtract Operation Examples E-3 Overflow Indicator Setting E-5

Examples E-5 Unsigned Numbers E-8 Signed Numbers E-I0

Appendix F. Reference Information F-l Address Key Register (AKR) F-l Condition Codes F-2

I/O Instruction Condition Codes F-2 Interrupt Condition Codes F-2 General Registers F-3

Interrupt Status Byte (ISB) F-3 DPC Devices F-3

Cycle-Steal Devices F-3 Level Status Register (LSR) F-4 Processor Status Word (PSW) F-4 Index X-I

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Processor Characteristics

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Chapter 1. Introduction

The IBM Series/l processor is a compact, general-purpose computer that has the following characteristics:

• Four priority interrupt levels-independent registers and status indicators for each level. Automatic and program-controlled level switching.

Instruction set that includes: stacking and linking facilities, multiply and divide, variable-field-length byte operations, and a variety of arithmetic and branching instructions.

Supervisor and problem states.

• Designed for mounting in standard 483 mm (19-inch) rack; some models do not require rack-mounting.

• Basic console standard in processor unit; programmer console optional.

• An address translator (not installed on all processors).

• A clock/comparator (not installed on all processors).

• Channel capability:

Asynchronous, multidropped channel.

- 256 input/output (I/O) devices can be addressed.

- Direct program control and cycle-steal operations.

The processor unit contains power and space for additional features. The IBM 4959 Input/Output Expansion Unit and the IBM 4965 Diskette ,Drive and I/O Expansion Unit are available for additional features.

Figure 1-1 shows a block diagram of an IBM Series/l processor and an IBM 4959 Input/Output Expansion Unit.

Four priority interrupt levels are implemented in the processor. Each level has an independent set of machine registers. Level switching can occur by program control or automatically upon acceptance of an I/O interrupt request. The interrupt mechanism provides 256 unique entry points for I/O devices.

The processor instruction set contains a variety of instruction types. These include: shift, register to register, register immediate, register to (or from) storage, bit manipulation, mUltiple register to storage, variable byte field, and storage to storage. Supervisor and problem states are implemented, with appropriate privileged instructions for the supervisor.

Introduction 1-1

1-2

IBM Series/1 Processor Translator*

Processor Storage

Channel Channel

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GA34-0152

Figure 1-1. Block diagram of an IBM Series/l processor and an IBM 4959 Input/Output Expansion Unit

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The basic console is intended for dedicated systems that are used in a basically unattended environment. Only minimal controls are provided. A programmer console, which can be added as a feature, provides a variety of indicators and controls for operator-oriented systems.

I/O devices are attached to the processor through the processor I/O channel. The channel directs the flow of information between the I/O devices, the processor, and main storage. This channel accommodates a maximum of 256 directly addressable devices.

The channel supports:

• Direct-program control operations. Each Operate I/O instruction transfers a byte or word of data between main storage and the device.

The operation mayor may not terminate in an interrupt.

• Cycle-steal operations. Each Operate I/O instruction initiates mUltiple data transfers between main storage and the device (65,535 bytes maximum). Cycle-steal operations are overlapped with processing operations and always terminate in an interrupt.

• Interrupt servicing. Interrupt requests from the devices, along with cycle-steal requests, are presented and polled concurrently with data transfers.

Input/Output Units, I/O Features, and Processor Options

A variety of I/O units and features, plus several processor options, are available for use with the Series/1 processor. For a list and description of system units and features, refer to the IBM Series/l System Selection

Guide, GA34-0143, and the IBM Series/l System Summary, GA34-0035.

Detailed information about I/O units and features can be found in separate publications. The order numbers for these publications are contained in the IBM Series/l Graphic Bibliography, GA34-0055.

Introduction 1-3

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Main Storage

Addressing Main Storage

Chapter 2. Processor Unit Description

Main storage holds data and instructions for applications to be processed on the system. The data and instructions are stored in units of information called bytes. Each byte consists of eight binary data bits plus a parity bit.

Odd parity by byte is maintained throughout storage; even parity causes a machine-check error. Formats shown in this manual exclude the parity bits because they are not a part of the data flow manipulated by the

instructions.

The bits within a byte are numbered consecutively, left to right, 0 through 7. When a format consists of multiple bytes, the numbering scheme is continued (for example, the bits in the second byte would be numbered 8 through 15). Leftmost bits are sometimes referred to as high-order or most-significant bits; rightmost bits are referred to as as low-order or least-significant bits.

Bytes can be handled separately or grouped together. A word is a group of two consecutive bytes, beginning on an even-address boundary, and is the basic building block of instructions. A doubleword is a group of four consecutive bytes, beginning on an even address boundary.

Each byte location in main storage is directly addressable. Byte locations in storage are numbered consecutively, starting with location 0; each number is considered to be the address of the corresponding byte. Storage addresses are 16-bit unsigned binary numbers. This permits a direct addressing range of 65,536 bytes.

When the storage address relocation translator is enabled, the logical address translates into a physical address that allows addressing beyond 65,536 bytes. Refer to individual processor publications for information regarding maximum fitted storage size.

Processor Unit Description 2-1

Instruction and Operand Address Boundaries

Byte

As previously stated, all storage addressing is defined by byte location.

Instructions can refer to bits, bytes, byte strings, words, or doublewords as data operands. All word and doubleword operand addresses must be on even-byte boundaries. All word and doubleword operand addresses point to the most-significant (leftmost) byte in the operand. Bit addresses are specified by a byte address and a bit displacement.

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To provide maximum addressing range, some instructions refer to a byte, word, or doubleword displacement that is added to the contents of a register. In these cases, the operand is a word and the register must contain an even-byte address for valid'results.

All instructions must be on an even-byte boundary.

The effective address for all branch type instructions must be on an even-byte boundary to be valid.

If the rules of even-byte addressing are violated, a program-check interrupt occurs with specification check set in the processor status word (PSW). The instruction is suppressed unless otherwise noted in the individual instruction description in Chapter 8.

31

Arithmetic and Logic Unit (ALU)

2-2 GA34-0152

The arithmetic and logic unit (ALU) contains the hardware circuits that perform addition, subtraction, and logical operations; such as, AND, OR, and Exclusive OR. The ALU performs address arithmetic as well as the operations required to process the instruction operands. Operands may be regarded, as signed or unsigned by the programmer. However, the ALU does not distinguish between them. Refer to "Numbering Representation"

in this chapter for a detailed discussion of signed or unsigned operands.

For many instructions, indicators are set to reflect the result of the ALU operation. Refer to "Indicator Bits" in this chapter for a detailed

discussion of indicator settings.

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Operands may be signed or unsigned depending on how they are used by the programmer. An unsigned number is a binary integer in which all bits contribute to the magnitude. A storage address is an example of an unsigned number. A signed number is one where the high-order bit is used to indicate the sign, and the remaining bits define the magnitude. Signed positive numpers are represented in true binary notation with the sign bit (high-order bit) set to O. Signed negative numbers are represented in two's complement notation with the sign bit (high-order bit) set to 1. The two's complement of a number is obtained by inverting each bit of the number and adding a 1 to the low-order bit position. Two's complement notation does not include a negative O. The maximum positive number consists of an all-l 's integer field with a sign bit of 0; the maximum negative number (the negative number with the greatest absolute value) consists of an all-O's integer field with a I-bit for the sign.

The following examples show:

• An unsigned 16-bit number

• A signed 16-bit positive number

• A signed 16-bit negative number Example of an unsigned 16-bit number:

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15 Bit position (The largest unsigned number representable in 16 bits.)

Example of a signed 16-bit positive number:

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+32767 7FFF

15 Bit position

(The largest positive signed number representable in 16 bits.)

Processor Unit Description 2-3

2-4 GA34-0152

When the number is positive, all bits to the left of the most-significant bit of the number, including the sign bit, are O's.

10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 Binary number

o L

Decimal value Hexadecimal value

+1 0001

15 Bit position

Example of a signed 16-bit negative number:

11 0 0 0 0 0 0 0 0 0 0 0 0 0001 Binary number Bit position

o

L

Decimal value Hexadecimal value

-32768 8000

15

(The largest negative signed number representable in 16 bits.)

Note: This form of representation yields a negative range of one more than the positive range.

When the number is negative, all bits to the left of the most-significant bit of the number, including the sign bit, are set to 1 'so

11 1 1 1 1 1 1 1 1 1 1 1 1 1 1 01 Binary number

o

L

Decimal value Hexadecimal value

-2 FFFE

15 Bit position

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0 0 0 0

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() 0 C) 0

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0 0 0

Registers

When a signed-number operand must be extended with high-order bits, the extension is achieved by prefixing a field with each bit set equal to the high-order bit of the operand.

Example of an 8-bit field extended to a 16-bit field:

11 1 1 1 1 1 1 0 11

o

L

Decimal val ue Hexadecimal value

11 1 1 1 1 1 1 1 1 1 1 1 1 1 0 11

o

L

Decimal value -3 Hexadecimal value FFFD

Binary number Bit position

-3 FD

Binary number Bit position

When performing the add and subtract operations, the processor does not regard the number as either signed or unsigned, but performs the

designated operation on the values presented. Whether a given add or subtract operation is to be regarded as a signed operation or an unsigned operation is determined by the programmer's view of the values being presented as operands. The carry indicator and the overflow indicator of the level status register (LSR) are changed on various operations to reflect the result of that operation. This allows the programmer to make result tests for the number representation involved. The carry and overflow indicator settings are explained in "Indicator Bits" in this chapter.

There are two general types of registers: system and level registers. The system registers are one-of-a-kind registers that retain information common to all priority-interrupt levels. The level registers, which are duplicated for each priority-interrupt level, retain information that must be saved when a level is preempted.

Information that pertains only to the current process is kept in registers common to all levels. The registers in each category are listed in this section.

Processor Unit Description 2-5

System Registers

Registers supplied on a system basis:

Processor status word (PSW) register Mask register (interrupt level)

Clock register(not installed on all processors) Comparator register(not installed on all processors) Segmentation registers (not installed on all processors)

Registers supplied on a system basis, using the programmer console:

Console data buffer register

• Current-instruction address register (CIAR)

• Storage address register (SAR)

• Console address key register

• Console stop-on-address register Registers supplied on a level basis:

• Address key register (AKR)

• General registers (eight per level)

• Instruction address register (IAR)

• Level status register (LSR)

• Floating-point registers (optional; not available for some processors) Note: For a specific level, the contents of the IAR, AKR, LSR, and the general registers are known as a level status block (LSB). The LSB is a 22-byte entity used by hardware and software for task control and task switching.

Processor Status Word (PSW) Register

Mask Register

2-6 GA34-0152

The processor status word (PSW) is a I6-bit register used to record error or exception conditions that may prevent further processing, and to hold certain flags that aid in error recovery. Error or exception conditions recorded in the PSW result in a class interrupt. Each bit in the PSW is described in detail in Chapter 3. The PSW can be accessed by using the Copy Processor Status and Reset (CPPSR) instruction. Refer to Chapter 8 for a detailed description of this instruction.

The mask register is used for control of interrupts. Bit 0 controls level 0, bit 1 controls level 1, and so on.

A I-bit enables interrupts on a level; a O-bit disables interrupts. For example, if bit 3 is set to aI, interrupts are enabled on level 3.

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Clock Register

Comparator Register

Segmentation Registers

Console Data Buffer Register

The clock register is a 32-bit register that is incremented at I-millisecond intervals. Refer to Chapter 6 for further information concerning the clock register.

The comparator register is a 32-bit register that is used in conjunction with the clock register to generate the clock class interrupt. Refer to Chapter 6 for further information concerning the comparator register.

A segmentation register is a register that changes a logical address to a physical address. Refer to Chapter 5 for further information concerning the segmentation registers.

The console data buffer is a I6-bit register associated with the programmer console. The contents of the console data buffer can be loaded into a specified general register by using the Copy Console Data Buffer (CPCON) instruction. Refer to Chapter 8 for a detailed description of this instruction. Refer to individual processor publication for further information concerning the programmer console.

Current-Instruction Address Register (CIAR)

Storage Address Register (SAR)

Console Address Key Register

The current-instruction address register (CIAR) is not addressable by software. It may be displayed from the programmer console. When the processor enters the stop state, the CIAR contains the address of the last instruction that was executed. Refer to "Stop State" under "Processor State Control" in this chapter for methods of entering stop state.

The storage address register (SAR) is not ,addressable by software. It is used for certain programmer console operations. SAR is a I6-bit register that contains the main-storage address for the last attempted processor storage cycle. Refer to individual processor publications for information concerning the programmer console.

The console address key register is not addressable by software. When the programmer console is installed, this register is used for certain console operations. Refer to individual processor publications for information concerning the programmer console.

Console Stop-On-Address Register

The console stop-on-address register is not addressable by software. When the programmer console is installed, this register is used for certain 'console operations. Refer to individual processor publications for information concerning the programmer console.

Processor Unit Description 2-7

Level Registers

Address Key Register (AKR)

General Registers

The address key register (AKR) is a 16-bit register that contains three address keys and an address-key control bit. Separate three-bit fields contain an address key for instruction address space, operand-l address space, and operand-2 address space.

Subsequently referred to simply as registers, the general registers are 16-bit registers available to the program for general purposes. Eight registers are provided for each level. The R- and RB fields in the instructions control the selection of these registers.

Instruction Address Register (JAR)

Level Status Register (LSR)

Floating-Point Registers

2-8 GA34-0152

The instruction address register (IAR) is a 16-bit register that holds the main storage address used to fetch an instruction. After an instruction has been fetched, the IAR is updated to point to the next instruction to be fetched.

Note: These registers are sometimes referred to as IARO, IAR1, IAR2, and IAR3. The numbers represent the priority level IAR.

The level status register (LSR) is a 16-bit register that holds:

• Indicator bits, which are set as a result of arithmetic, logical, or I/O operations

• A supervisor state bit

• An in-process bit

• A trace bit

• A summary mask bit

These bits are discussed further in the following paragraphs. Seven other bits in the LSR are not used and are always set to O's.

A floating-point register is a 64-bit register. The floating-point feature includes four 64-bit floating-point registers for each of the four priority interrupts levels in the processor. Refer to Chapter 7 for a detailed discussion of the floating-point feature.

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Indicator Bits

The indicators are located in bits 0-4 of the level status register (LSR).

Figure 2-1 shows the indicators and how they are set for arithmetic operations. The indicator bits are .changed or not changed depending on the instruction being executed. Some instructions do not affect the indicators, other instructions change all of the indicators, and still other instructions change only specific indicators. Refer to the individual

instruction descriptions in Chapter 8 for the indicators that are changed by each instruction.

Level status register (LSR)

o

~

Negative - Set to 1 if bit 0 of result is 1;

otherwise, set to O.

'--- Overflow - Set to 1 if result of arithmetic operation (with the operands regarded as signed numbers) cannot be represented as a signed number in the operand size speci- fied; otherwise, set to O.

' - - - Carry - Set to 1 if the result of add or sub- tract operations (with the operands regarded as unsigned numbers) cannot be represented as an unsigned number in the operand size specified; otherwise, set to O.

' - - - Even - Set to 1 if the low-order bit of the result is 0; otherwise, set to O.

Figure 2-1. How indicators are set for signed and unsigned (logical) operations

The indicators are changed in a specialized manner for certain operations.

These operations are described briefly. Additional information is provided in subsequent paragraphs for those operations where more detail is required.

Add, subtract, or logical operations. The even, negative, and zero indicators are result indicators. For add and subtract operations, the carry and overflow indicators are changed to provide information for both signed and unsigned number representations.

• Multiply and divide operations. Signed number operands are always assumed for these operations. The carry indicator is used to provide a divide by 0 indication for the divide instruction. The overflow

indicator defines an unrepresentable product for multiply operations.

Refer to the individual instruction descriptions in Chapter 8.

Priority interrupts and input/output operations. The even, carry, and overflow indicators are used to form a three-bit condition code that is set as a binary value.

Processor Unit Description 2-9

• Compare operations. The indicators are set in the same manner as in a subtract operation.

• Shift operations. The carry and overflow indicators have a special meaning for shift left logical operations.

• Complement operations. The overflow indicator is set if an attempt is made to complement the maximum negative number. This number is not representable.

Set Indicators (SEIND) and Set Level Block (SELB) instructions. All indicators are changed by the data associated with these instructions.

Even, Negative, and Zero Result Indicators

The even, negative, and zero indicators are called the result indicators. A positive result is indicated when the zero and negative indicators are both off (set to D's). These indicators are set to reflect the result of the last arithmetic or logical operation performed. A logical operation in this sense includes data movement instructions. Refer to the individual instruction descriptions in Chapter 8 for the indicators changed for specific

instructions.

Even, Carry, and Overflow Indicators-Condition Code for Input/Output Operations

The even, carry, and overflow indicators contain the I/O condition code following the execution of an Operate I/O instruction and following an I/O interrupt.

These indicators are used to form a three-bit binary number that results in a condition code value. For additional information about condition codes, refer to Branch on Condition Code (BCC) and Branch on Not Condition Code (BNCC) instructions in Chapter 8 and "I/O Condition Codes and Status Information" in Chapter 4.

Carry and Overflow Indicators-Add and Subtract Operations

Corry Indicator Setting

Overflow Indicator Setting

2-10 GA34-0152

A common set of add and subtract integer operations performs both signed and unsigned arithmetic. Whether a given add or subtract operation is to be regarded as a signed operation or an unsigned operation is

determined by the programmer's view of the values being presented as operands. The carry and overflow indicators are set to reflect the results for both cases.

The carry indicator is used to signal.overflow of the result when operands are presented as unsigned numbers.

The overflow indicator is used to signal overflow of the result when the operands are presented as signed numbers.

Note: Appendix E explains the meaning of these indicators for signed and unsigned numbers. The appendix also provides examples for setting the carry and overflow indicators.

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Carry and Overflow Indicators-Shift Operations

Indicators-Compare Operations

The carry and overflow indicators are changed for shift left logical operations and shift left and test operations. These operations affect the indicators as follows:

• The carry indicator is set to reflect the value of the last bit shifted out of the target register (register where bits are being shifted).

• The overflow indicator is set to 1 if bit 0 of the target register was changed during the shift; otherwise, it is set to O.

A compare operation sets the indicators in the same manner as a subtract operation. The even, negative, and zero indicators reflect the result. The carry and overflow indicators are set as described previously.

Compare instructions provide a test between two operands (without altering either operand) so that conditional branch and jump instructions may be used to control the programming logic flow. The conditions specified in branch and jump instructions are named such that, when the condition of the "subtracted from" operand relative to the other operand is true, the jump or branch occurs; otherwise, the next sequential

instruction is executed. This is illustrated in the following example.

Example of compare operation:

Instruction Assembler

name mnemonic Operands

Compare word CW Reg 3, Reg 4

Op code Function

o

o

0 4 5 7 1011 15

~"'-v-'

Reg 3 Reg 4

In this example, the contents of register 3 are subtracted from register 4:

Decimal

Unsigned Signed Reg 4 contents 0000 0000 0000 0010 2

Reg 3 contents 1111111111\111011 65531

+2 -5

Subtract result -65529 +7

Machine operation:

0000 0000 0000 0010 Minuend

Subtrahend Constant

0000 0000 0000 0100 one's complement for two's complement Result 0000 0000 0000 0111

Processor Unit Description 2-11